Systems and methods involving hybrid quantum machines, aspects of quantum information technology and/or other features

Abstract

Systems and methods involving quantum machines, hybrid quantum machines, aspects of quantum information technology and/or other features are disclosed. In one exemplary implementation, a system is provided comprising a quantum register that stores quantum information using qubits, wherein the qubits are configured to store the quantum information using particles or objects arranged in a lattice of quantum gates, a clock that provides a clock cycle to the quantum register, and a qubit-tie computing component coupled to the quantum register, wherein the qubit-tie computing component is configured to shift the quantum information between the qubits, wherein the system stores the qubits in different states using physical qualities, which may define qubits that are configured to be entangled and superposed at a same time. Further, the quantum register may comprise an entanglement component, and/or the qubit-tie computing component may comprise a superposition component.

The invention claimed is: 
     
       1. A hybrid quantum computer system comprising:
 a hybrid quantum processor comprising at least one quantum processor and a quantum information controller; 
 a peripheral component interconnect (PCI) express bus coupled to the hybrid quantum processor; 
 a memory storage system comprising random access memory and coupled to the PCI express bus; and 
 a plurality of pre-processing units and a plurality of post-processing units, both of which are comprised of different types of processing units and coupled to the PCI express bus; 
 wherein the system is based on a memory centric computing architecture and is configured to connect the different types of processing units together with the at least one quantum processor via the PCI express bus, wherein each of the at least one quantum processor is fully addressable, the memory centric computing architecture characterized by:
 memory banks, of the random access memory, being configured to be directly addressed by the PCI express bus, both from the plurality of pre-processing units and the plurality of post-processing units and from the hybrid quantum processor, simultaneously, such that the memory storage system serves as a centralized memory architecture therebetween; and 
 an inbuilt cache coherence that acknowledges writes only when data has been physically written and is available for physical read operations of another device. 
 
 
     
     
       2. The system of  claim, 1 , wherein one or both of: the qubits are configured to store the quantum information over a same time period defined by one or more cycles of the clock; and/or the qubits are configured to transition into different states per time unit as defined by the clock cycle. 
     
     
       3. The system of  claim, 1 , further comprising:
 a qubit-tie computing component coupled to the quantum register, the qubit-tie computing component comprising a superposition component; 
 wherein the qubit-tie computing component is coupled to the quantum register via an entanglement component and the superposition component. 
 
     
     
       4. The system of  claim, 1 , further comprising: a gate control unit that performs manipulations on the qubits that configure the qubits such that the qubits are immune from disturbances. 
     
     
       5. The system of  claim 4 , further comprising an error correcting component within the gate control unit which corrects errors on one or more of the qubits. 
     
     
       6. The system of  claim 3 , wherein the qubit-tie computing component comprises an additional quantum system, positioned between a read/write component and the quantum register. 
     
     
       7. The system of  claim 1 , further comprising one or more additional components implementing at least one of a decoherence aspect, a fidelity aspect, and/or a complexity/manifold aspect to facilitate implementation of a quantum processing unit (QPU). 
     
     
       8. The system of  claim 1 , wherein the qubits are implemented as one or more elementary particles, and wherein the elementary particles are configured to store one or more states and/or characteristics and are confined to preventing interaction with external elements that alter the one or more states and/or characteristics. 
     
     
       9. The system of  claim 1 , wherein the qubits are implemented as one or more elementary particles, and wherein the elementary particles comprise one or more simple elementary particles defined as being superconducting electrons, vacuum isolated protons, H−, Het, and/or other light ions respectively anions. 
     
     
       10. The system of  claim 1 , wherein the qubits are implemented as one or more elementary particles, and wherein the elementary particles are: trapped in artificial force fields, and shielded from any incoming particle or quasi-particle. 
     
     
       11. The system of  claim 1 , wherein the qubits are implemented as one or more elementary particles and the elementary particles are trapped in artificial force fields; wherein the artificial force fields include one or more microscopic force fields; and wherein, optionally, the microscopic force field include and/or involve atom bodies in a crystal provided to electrons in a conduction band within a high temperature superconductor. 
     
     
       12. The system of  claim 1 , further comprising:
 a quantum register that stores quantum information using qubits. 
 
     
     
       13. The system of  claim 1 , wherein the system is configured to provide a cache coherent dataflow between heterogenous processing units via the memory centric computing architecture. 
     
     
       14. The system of  claim 1 , wherein the system further comprises an inbuilt cache coherence that acknowledges writes only when the data has been physically written and is available for physical read operations of another device. 
     
     
       15. The system of  claim, 1  wherein two or more of:
 the qubits are configured to be entangled with one or more different systems and/or entities external to the system; 
 the qubits are configured to be transitioned into superposed states defined by characteristics of the particles or objects; and/or 
 the system stores the qubits in different states using physical qualities, wherein the physical qualities define qubits that are configured to be entangled and superposed at a same time. 
 
     
     
       16. The system of  claim 1 , wherein the qubits are configured to be entangled with one or more different systems and/or entities external to the system. 
     
     
       17. A hybrid quantum processor system comprising:
 a memory storage system comprising random access memory; 
 a peripheral component interconnect (PCI) express bus coupled to the memory storage system; 
 a plurality of pre-processing units and a plurality of post-processing units, both of which are comprised of different types of processing units and coupled to the PCI express bus; and 
 a hybrid quantum processor coupled to the PCI express bus and comprising:
 an arithmetic and logic unit (ALU) comprising a plurality of quantum gates that store first quantum information; and 
 one or more gate creation units and/or gate control units coupled to the ALU and configured for one or both of entanglement and/or superposition with second quantum information stored on particles or objects external to the ALU; 
 
 wherein the PCI express bus couples the one or more gate creation units and/or gate control units to the particles or objects external to the ALU, wherein, as a function of the first quantum information being coupled to the second quantum information, the ALU is configured to provide the plurality of quantum gates as ubiquitous types of gates, and thereby yield universal quantum machine codes, and 
 wherein the system has a memory centric computing architecture characterized by:
 memory banks, of the random access memory, being configured to be directly addressed by the PCI express bus, both from the plurality of pre-processing units and the plurality of post-processing units and from the hybrid quantum processor, simultaneously, such that the memory storage system serves as a centralized memory architecture therebetween; and 
 an inbuilt cache coherence that acknowledges writes only when data has been physically written and is available for physical read operations of another device. 
 
 
     
     
       18. The system of  claim 17 , further comprising one or more additional components implementing at least one of a decoherence aspect, a fidelity aspect, and/or a complexity/manifold aspect to facilitate implementation of a quantum processing unit (QPU). 
     
     
       19. A system comprising:
 a memory storage system comprising random access memory; 
 a peripheral component interconnect (PCI) express bus coupled to the memory storage system; 
 a plurality of pre-processing units and a plurality of post-processing units, both of which are comprised of different types of processing units and coupled to the PCI express bus; and 
 a hybrid quantum processor coupled to the PCI express bus and comprising an information controller and one or more quantum processing units, wherein each of the quantum processing units comprises:
 a quantum register that stores quantum information using qubits, wherein the qubits are configured to store the quantum information using particles or objects arranged in a lattice of quantum gates; 
 a clock that provides a clock cycle to the quantum register; and 
 a qubit-tie computing component coupled to the quantum register, wherein the qubit-tie computing component is configured to shift the quantum information between the qubits; and 
 a bus control unit that receives and is configured to cache the quantum information into classical memory in order to be further transferred to the PCI express bus; 
 
 wherein the system stores the qubits in different states using physical qualities; and 
 wherein the system has a memory centric computing architecture characterized by:
 memory banks, of the random access memory, being configured to be directly addressed by the PCI express bus, both from the plurality of pre-processing units and the plurality of post-processing units and from the hybrid quantum processor, simultaneously, such that the memory storage system serves as a centralized memory architecture therebetween; and 
 an inbuilt cache coherence that acknowledges writes only when data has been physically written and is available for physical read operations of another device. 
 
 
     
     
       20. The system of  claim 19 , wherein the quantum register comprises an entanglement component, and wherein the qubits are configured to be entangled with one or more different systems and/or entities external to the system. 
     
     
       21. The system of  claim 19 , the qubit-tie computing component comprising a superposition component, and wherein the qubits are configured to be transitioned into superposed states defined by characteristics of the particles or objects. 
     
     
       22. The system of  claim 19 , wherein the physical qualities define qubits that are configured to be entangled and superposed at a same time. 
     
     
       23. The system of  claim 19 , wherein the qubits are configured to store the quantum information over a same time period defined by one or more cycles of the clock. 
     
     
       24. The system of  claim 19 , wherein the qubits are configured to transition into different states per time unit as defined by the clock cycle. 
     
     
       25. The system of  claim 19 , wherein the qubit-tie computing component is coupled to the quantum register via an entanglement component. 
     
     
       26. The system of  claim 19 , wherein the qubit-tie computing component is coupled to the quantum register via a superposition component. 
     
     
       27. The system of  claim 19 , wherein the qubit-tie computing component is coupled to the quantum register via an entanglement component and a superposition component. 
     
     
       28. The system of  claim 19 , further comprising:
 a gate control unit that performs manipulations on the qubits that configure the qubits such that the qubits are immune from disturbances. 
 
     
     
       29. The system of  claim 28 , further comprising an error correcting component within the gate control unit which corrects errors on one or more of the qubits. 
     
     
       30. The system of  claim 19 , wherein the qubit-tie computing component comprises an additional quantum system, positioned between a read/write component and the quantum register. 
     
     
       31. The system of  claim 19 , further comprising one or more additional components implementing at least one of a decoherence aspect, a fidelity aspect, and/or a complexity/manifold aspect to facilitate implementation of a quantum processing unit (QPU). 
     
     
       32. The system of  claim 19 , wherein the qubits are implemented as one or more elementary particles, and wherein the elementary particles are configured to store one or more states and/or characteristics and are confined to preventing interaction with external elements that alter the one or more states and/or characteristics. 
     
     
       33. The system of  claim 19 , wherein the qubits are implemented as one or more elementary particles, and wherein the elementary particles comprise one or more simple elementary particles defined as being superconducting electrons, vacuum isolated protons, H−, He+, and/or other light ions respectively anions. 
     
     
       34. The system of  claim 19 , wherein the qubits are implemented as one or more elementary particles, and wherein the elementary particles are: trapped in artificial force fields, and shielded from any incoming particle or quasi-particle. 
     
     
       35. The system of  claim 19 , wherein the qubits are implemented as one or more elementary particles and the elementary particles are trapped in artificial force fields. 
     
     
       36. The system of  claim 35 , wherein the artificial force fields include one or more microscopic force fields. 
     
     
       37. The system of  claim 35 , wherein the microscopic force field include and/or involve atom bodies in a crystal provided to electrons in a conduction band within a high temperature superconductor. 
     
     
       38. The system of  claim 1 , further comprising one or more additional components implementing two or more of a decoherence aspect, a fidelity aspect, and/or a complexity/manifold aspect to facilitate implementation of a quantum processing unit (QPU). 
     
     
       39. The system of  claim 1 , wherein the qubits are configured to be transitioned into superposed states defined by characteristics of the particles or objects. 
     
     
       40. The system of  claim 1 , currently amended wherein the system stores the qubits in different states using physical qualities. 
     
     
       41. The system of  claim 40 , wherein the physical qualities define qubits that are configured to be entangled and superposed at a same time. 
     
     
       42. The system of  claim 1  wherein the quantum register comprises an entanglement component, and wherein the qubits are configured to be entangled with one or more different systems and/or entities external to the system. 
     
     
       43. The system of  claim 1 , further comprising:
 a qubit-tie computing component coupled to the quantum register, wherein the qubit-tie computing component comprising a superposition component, and wherein the qubits are configured to be transitioned into superposed states defined by characteristics of the particles or objects. 
 
     
     
       44. The system of  claim 17 , further comprising:
 a quantum register that stores quantum information using qubits. 
 
     
     
       45. The system of  claim 44 , wherein the qubits are configured to be entangled with one or more different systems and/or entities external to the system. 
     
     
       46. The system of  claim 44 , wherein the qubits are configured to be transitioned into superposed states defined by characteristics of the particles or objects. 
     
     
       47. The system of  claim 44 , wherein the system stores the qubits in different states using physical qualities, wherein the physical qualities define qubits that are configured to be entangled and superposed at a same time. 
     
     
       48. The system of  claim 44 , wherein the qubits are configured to store the quantum information over a same time period defined by one or more cycles of the clock. 
     
     
       49. The system of  claim 44 , wherein the qubits are configured to transition into different states per time unit as defined by the clock cycle. 
     
     
       50. The system of  claim 44 , wherein two or more of:
 the qubits are configured to be entangled with one or more different systems and/or entities external to the system; 
 the qubits are configured to be transitioned into superposed states defined by characteristics of the particles or objects; and/or 
 the system stores the qubits in different states using physical qualities, wherein the physical qualities define qubits that are configured to be entangled and superposed at a same time. 
 
     
     
       51. The system of  claim 44 , further comprising:
 a qubit-tie computing component coupled to the quantum register, the qubit-tie computing component comprising a superposition component. 
 
     
     
       52. The system of  claim 51 , wherein the qubit-tie computing component is coupled to the quantum register via an entanglement component. 
     
     
       53. The system of  claim 51 , wherein the qubit-tie computing component is coupled to the quantum register via a superposition component. 
     
     
       54. The system of  claim 51 , wherein the qubit-tie computing component is coupled to the quantum register via an entanglement component and a superposition component. 
     
     
       55. The system of  claim 51 , wherein the qubit-tie computing component comprises an additional quantum system, positioned between a read/write component and the quantum register. 
     
     
       56. The system of  claim 44 , further comprising:
 a gate control unit that performs manipulations on the qubits that configure the qubits such that the qubits are immune from disturbances. 
 
     
     
       57. The system of  claim 56 , further comprising an error correcting component within the gate control unit which corrects errors on one or more of the qubits. 
     
     
       58. The system of  claim 17 , further comprising one or more additional components implementing two or more of a decoherence aspect, a fidelity aspect, and/or a complexity/manifold aspect to facilitate implementation of a quantum processing unit (QPU). 
     
     
       59. The system of  claim 44 , wherein the qubits are implemented as one or more elementary particles, and wherein the elementary particles are configured to store one or more states and/or characteristics and are confined to preventing interaction with external elements that alter the one or more states and/or characteristics. 
     
     
       60. The system of  claim 44 , wherein the qubits are implemented as one or more elementary particles, and wherein the elementary particles comprise one or more simple elementary particles defined as being superconducting electrons, vacuum isolated protons, H−, He+, and/or other light ions respectively anions. 
     
     
       61. The system of  claim 44 , wherein the qubits are implemented as one or more elementary particles, and wherein the elementary particles are: trapped in artificial force fields, and shielded from any incoming particle or quasi-particle. 
     
     
       62. The system of  claim 44 , wherein the qubits are implemented as one or more elementary particles and the elementary particles are trapped in artificial force fields. 
     
     
       63. The system of  claim 62 , wherein the artificial force fields include one or more microscopic force fields. 
     
     
       64. The system of  claim 62 , wherein the microscopic force field include and/or involve atom bodies in a crystal provided to electrons in a conduction band within a high temperature superconductor. 
     
     
       65. The system of  claim 17 , wherein the system is configured to provide a cache coherent dataflow between heterogenous processing units via the memory centric computing architecture. 
     
     
       66. The system of  claim 17 , wherein the system further comprises an inbuilt cache coherence that acknowledges writes only when the data has been physically written and is available for physical read operations of another device.