Memory usage configurations for integrated circuit devices having analog inference capability

Abstract

An integrated circuit device having a memory cell array with first layers of memory cells configured for operations of multiplication and accumulation. Each pair of closest layers among the first layers are configured to be separate by at least one layer in second layers of memory cells, where access to, or usages of, the second layers can be restricted or limited to prevent activities in the second layers from corrupting the weight programming in the first layers.

What is claimed is: 
     
       1. A device, comprising:
 a memory cell array having a plurality of layers of memory cells, wherein each respective memory cell in the memory cell array has a threshold voltage programmable in a first mode to perform operations of multiplication and accumulation; 
 a register; and 
 a logic circuit; 
 wherein the logic circuit is configured to:
 map, based on the register having first data identifying a first configuration, a first set of logical layer addresses to address a first subset of the plurality of layers, wherein each respective pair of layers in the first subset are separated by at least one layer not in the first subset; 
 program, in the first mode and based on the register having the first data, thresholds voltages of memory cells in the first subset of the plurality of layers to represent weight data; and 
 limit, based on the register having the first data, access to the at least one layer not in the first subset. 
 
 
     
     
       2. The device of  claim 1 , wherein the logic circuit is configured to cause, based on the register having the first data, the at least one layer not in the first subset inaccessible via logical layer addresses. 
     
     
       3. The device of  claim 1 , wherein the logic circuit is further configured to:
 map, based on the register having the first data, a second set of logical layer addresses to address a second subset of the plurality of layers, wherein the second subset does not include any layer in the first subset, and the second subset includes the at least one layer separating the respective pair of layers in the first subset. 
 
     
     
       4. The device of  claim 3 , wherein the logic circuit is further configured to:
 map, based on the register having second data identifying a second configuration, the first set of logical layer addresses to address the second subset of the plurality of layers, and the second set of logical layer addresses to address the first subset of the plurality of layers; 
 wherein the second subset is configured, based on the register storing the first data, to be accessed at a frequency lower than the first subset. 
 
     
     
       5. The device of  claim 4 , wherein the logic circuit is further configured to:
 program, based on the register having the first data, threshold voltages of memory cells in the second subset in a second mode, different from the first mode, to store data. 
 
     
     
       6. The device of  claim 5 , wherein the respective memory cell is configured to output, when programmed in the first mode and applied a predetermined read voltage:
 a predetermined amount of current to represent a weight of one stored in the respective memory cell; or 
 a negligible amount of current to represent a weight of zero stored in the respective memory cell; and 
 wherein the threshold voltage of the respective memory cell is positioned within a voltage region among a plurality of voltage regions pre-associated with a plurality of values respectively when programmed in the second mode; and 
 wherein the respective memory cell in the memory cell array is configured to store one bit per cell when programmed in the first mode; and the respective memory cell in the memory cell array is configured to store more than one bit per cell when programmed in the second mode. 
 
     
     
       7. The device of  claim 4 , wherein the logic circuit is further configured to:
 program, based on the register having the first data, threshold voltages of memory cells in the second subset in the first mode, to store a redundant copy of the weight data. 
 
     
     
       8. The device of  claim 7 , wherein the logic circuit is further configured to:
 perform redundant computations using the weight data stored in the first subset and the second subset in parallel to generate redundant results; 
 compare the redundant results; 
 reprogram or refresh the second subset in response to a detection of a mismatch between the redundant result; and 
 update the register to store the second data, after the second subset is reprogrammed or refreshed following the detection of the mismatch. 
 
     
     
       9. The device of  claim 4 , wherein the logic circuit is further configured to:
 program, based on the register having the first data, threshold voltages of memory cells in the second subset in the first mode, to store an inverted version of the weight data; 
 perform computations using the weight data stored in the first subset and the inverted version of the weight data in the second subset in parallel to generate redundant results; and 
 compare the redundant results to detect corruption in weight programming. 
 
     
     
       10. A method, comprising:
 writing, into a register of an integrated circuit device, first data identifying a first configuration of using a plurality of layers of memory cells in a memory cell array in the integrated circuit device; 
 mapping, based on the register having the first data, a first set of logical layer addresses to address a first subset of the plurality of layers, wherein each respective pair of layers in the first subset are separated by at least one layer not in the first subset; 
 programming, in a first mode and based on the register having the first data, thresholds voltages of memory cells in the first subset of the plurality of layers to represent weight data; 
 performing, using the first subset, operations of multiplication and accumulation; and 
 limiting, based on the register having the first data, usages of the at least one layer not in the first subset to reduce disturbs on the thresholds voltages of memory cells in the first subset. 
 
     
     
       11. The method of  claim 10 , wherein each respective memory cell in the memory cell array is configured to output, when a threshold voltage of the respective memory cell is programmed in the first mode and the respective memory cell is applied a predetermined read voltage:
 a predetermined amount of current to represent a weight of one stored in the respective memory cell; or 
 a negligible amount of current to represent a weight of zero stored in the respective memory cell; 
 wherein the threshold voltage of the respective memory cell is positioned within a voltage region among a plurality of voltage regions pre-associated with a plurality of values respectively when programmed in a second mode; and 
 wherein the respective memory cell in the memory cell array is configured to store one bit per cell when programmed in the first mode; and the respective memory cell in the memory cell array is configured to store more than one bit per cell when programmed in the second mode. 
 
     
     
       12. The method of  claim 11 , wherein the limiting of the usages includes rendering, based on the register having the first data, the at least one layer not in the first subset inaccessible via logical layer addresses. 
     
     
       13. The method of  claim 11 , further comprising:
 mapping, based on the register having the first data, a second set of logical layer addresses to address a second subset of the plurality of layers, wherein the second subset does not include any layer in the first subset, and the second subset includes the at least one layer separating the respective pair of layers in the first subset; and 
 mapping, based on the register having second data identifying a second configuration, the first set of logical layer addresses to address the second subset of the plurality of layers, and the second set of logical layer addresses to address the first subset of the plurality of layers; 
 wherein the limiting of the usages includes accessing, based on the register storing the first data, the second subset less frequently lower than the first subset. 
 
     
     
       14. The method of  claim 13 , further comprising:
 programming, based on the register having the first data, threshold voltages of memory cells in the second subset in a second mode, different from the first mode, to store data. 
 
     
     
       15. The method of  claim 13 , further comprising:
 programming, based on the register having the first data, threshold voltages of memory cells in the second subset in the first mode, to store a redundant copy of the weight data. 
 
     
     
       16. The method of  claim 15 , further comprising:
 performing redundant computations using the weight data stored in the first subset and the second subset in parallel to generate redundant results; 
 comparing the redundant results; 
 reprogramming or refreshing the second subset in response to a detection of a mismatch between the redundant result; 
 updating the register to store the second data, after the second subset is reprogrammed or refreshed following the detection of the mismatch; 
 storing historic data representative of time gaps between reprogramming or refreshing of the weight data and detection of corruption in weight programming; and 
 computing a prediction of a time to a next detection of corruption in weight programming based on the historic data. 
 
     
     
       17. The method of  claim 13 , further comprising:
 programming, based on the register having the first data, threshold voltages of memory cells in the second subset in the first mode, to store an inverted version of the weight data; 
 performing computations using the weight data stored in the first subset and the inverted version of the weight data in the second subset in parallel to generate redundant results; and 
 comparing the redundant results to detect corruption in weight programming. 
 
     
     
       18. An apparatus, comprising:
 an integrated circuit die having a memory cell array configured in a plurality of layers having a first subset and a second subset, the first subset and the second subset being mutually exclusive, each respective pair of layers in the first subset being separated by at least one layer in the second subset; and 
 an integrated circuit die having a logic circuit; 
 wherein the apparatus is configured to program threshold voltages of memory cells in the first subset to represent weight data of an artificial neural network; 
 wherein the logic circuit is configured to use the first subset to perform operations of multiplication and accumulation of computations of the artificial neural network; and 
 wherein the apparatus is configured to limit usages of the second subset to reduce disturbs on the threshold voltages of memory cells in the first subset. 
 
     
     
       19. The apparatus of  claim 18 , further comprising:
 an integrated circuit die having an image sensing pixel array configured to generate image data as an input to the artificial neural network; and 
 an integrated circuit package configured to enclose at least the memory cell array and the logic circuit. 
 
     
     
       20. The apparatus of  claim 19 , wherein each respective layer in the first subset has a plurality of columns of memory cells having output currents connected to a plurality of bitlines respectively, the respective layer having rows of memory cells connected to wordlines respectively to receive applied voltages;
 wherein the respective layer has wordlines selected according to a column of input bits to have a predetermined read voltage applied concurrently for bitwise multiplication to output currents into the bitlines; and 
 wherein the apparatus further comprises analog to digital converters configured to digitize summed currents in the bitlines as multiple of the predetermined amount of current.