Semiconductor memory

Abstract

A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.

What is claimed is: 
     
       1. A semiconductor memory device comprising:
 a plurality of first conductive layers stacked above a substrate and spaced apart from each other in a first direction intersecting a surface of the substrate, each of the first conductive layers extending in a second direction intersecting the first direction; 
 a second conductive layer extending in the second direction above the first conductive layers; 
 a third conductive layer extending in the second direction above the first conductive layers, the third conductive layer being arranged adjacently to the second conductive layer in a third direction intersecting the first direction and the second direction; 
 a plurality of first pillars extending through the first conductive layers and the second conductive layer in the first direction, intersections of the first pillars with at least one of the first conductive layers functioning as first memory cells and intersections of the first pillars with the second conductive layer functioning as first select transistors; 
 a plurality of second pillars extending through the first conductive layers and the third conductive layer in the first direction, intersections of the second pillars with at least one of the first conductive layers functioning as second memory cells and intersections of the second pillars with the third conductive layer functioning as second select transistors; 
 a plurality of third pillars extending through the first conductive layers in the first direction and extending between the second conductive layer and the third conductive layer; 
 a first insulator provided in a first slit extending in the first and second directions along one side of the first conductive layers in the third direction, the first insulator continuously covering a bottom surface of the first slit and both side surfaces of the first slit extending in the second direction; 
 a second insulator provided in a second slit extending in the first and second directions along the other side of the first conductive layers in the third direction, the second insulator continuously covering a bottom surface of the second slit and both side surfaces of the second slit extending in the second direction; and 
 a third insulator provided in a third slit extending in the first and third directions, one end of the third slit in the third direction being coupled to one end of the first slit in the second direction and the other end of the third slit in the third direction being coupled to one end of the second slit in the second direction, and the third insulator being in contact with ends of the first conductive layers in the second direction. 
 
     
     
       2. The semiconductor memory device according to  claim 1 , wherein
 the one side of the first conductive layers in the third direction is in contact with the first insulator in the first slit, and 
 the other side of the first conductive layers in the third direction is in contact with the second insulator in the second slit. 
 
     
     
       3. The semiconductor memory device according to  claim 1 , wherein intersections of the third pillars with any one of the first conductive layers function as neither memory cells. 
     
     
       4. The semiconductor memory device according to  claim 1 , wherein
 each of the first pillars is electrically connected to a bit line, 
 each of the second pillars is electrically connected to a bit line, and 
 none of the third pillars is electrically connected to any bit line. 
 
     
     
       5. The semiconductor memory device according to  claim 1 , wherein
 one side of the third pillars in the third direction is in contact with the second conductive layer, and 
 the other side of the third pillars in the third direction is in contact with the third conductive layer. 
 
     
     
       6. The semiconductor memory device according to  claim 1 , further comprising:
 a fourth insulator provided in a fourth slit extending in the first and second directions between the second conductive layer and the third conductive layer, the fourth insulator covering a bottom surface of the fourth slit and both side surfaces of the fourth slit extending in the second direction, the fourth slit extending into the third pillars in the first direction. 
 
     
     
       7. The semiconductor memory device according to  claim 6 , wherein the fourth insulator is in contact with one side of the second conductive layer in the third direction and with one side of the third conductive layer in the third direction. 
     
     
       8. The semiconductor memory device according to  claim 6 , wherein the fourth insulator does not extend through any of the first conductive layers. 
     
     
       9. The semiconductor memory device according to  claim 6 , wherein the fourth slit is not coupled to the first slit, the second slit, and the third slit. 
     
     
       10. The semiconductor memory device according to  claim 6 , further comprising:
 a fifth insulator provided in a fifth slit extending in the first and second directions between the fourth slit and the second slit, the fifth insulator covering a bottom surface of the fifth slit and both side surfaces of the fifth slit extending in the second direction. 
 
     
     
       11. The semiconductor memory device according to  claim 10 , wherein the fifth insulator extends through the plurality of first conductive layers. 
     
     
       12. The semiconductor memory device according to  claim 10 , wherein the fifth slit is not coupled to the first slit, the second slit, the third slit, and the fourth slit. 
     
     
       13. The semiconductor memory device according to  claim 10 , wherein one end of the fifth slit in the second direction is spaced apart from the third slit, with the first conductive layers there between.