Methods for forming recesses in source/drain regions and devices formed thereof

Abstract

Embodiments disclosed herein relate generally to methods for forming recesses in epitaxial source/drain regions for forming conductive features. In some embodiments, the recesses are formed in a two-step etching process including an anisotropic etch to form a vertical opening and an isotropic etch to expand an end portion of the vertical opening laterally and vertically. The recesses can have increased contact area between the source/drain region and the conductive feature, and can enable reduced resistance therebetween.

What is claimed is: 
     
       1. A semiconductor structure comprising:
 an epitaxial region adjacent a gate electrode; 
 one or more dielectric layers over the epitaxial region; and 
 a conductive feature extending through the one or more dielectric layers and contacting the epitaxial region, wherein in a first cross section the epitaxial region extends over a portion of the conductive feature in the epitaxial region an upper surface of the conductive feature, wherein the conductive feature has a widest width in a second cross section at an upper surface of the epitaxial region, wherein the first cross section is perpendicular to a longitudinal axis of the gate electrode, wherein the second cross section is perpendicular to the first cross section. 
 
     
     
       2. The semiconductor structure of  claim 1 , wherein a width of the conductive feature narrows as the conductive feature extends into the one or more dielectric layers from an upper surface of the one or more dielectric layers. 
     
     
       3. The semiconductor structure of  claim 1 , wherein the conductive feature has a widest width in the first cross section offset from an upper surface of the epitaxial region. 
     
     
       4. The semiconductor structure of  claim 1 , wherein the epitaxial region is an n-type region, wherein the conductive feature has a lateral expansion in the epitaxial region in a range between 2 nm and 10 nm. 
     
     
       5. The semiconductor structure of  claim 1 , wherein the epitaxial region is a p-type region, wherein the conductive feature has a lateral expansion in the epitaxial region in a range between 2 nm and 5 nm. 
     
     
       6. The semiconductor structure of  claim 1 , wherein the conductive feature comprises a barrier layer and a fill material. 
     
     
       7. The semiconductor structure of  claim 1 , wherein the conductive feature extends into the epitaxial region to a depth in a range from 5% to 50% of a height of the epitaxial region in the first cross section. 
     
     
       8. A semiconductor structure comprising:
 a first source/drain region and a second source/drain region in an active area on a substrate; 
 one or more dielectric layers over the first source/drain region; and 
 a conductive feature extending through the one or more dielectric layers to the first source/drain region, the conductive feature extending lower than a first uppermost surface of the first source/drain region in a first cross-sectional view and lower than a second uppermost surface of the first source/drain region in a second cross-sectional view, the first cross-sectional view being perpendicular to a current flow direction between the first source/drain region and the second source/drain region, the second cross-sectional view being parallel to a current flow, the conductive feature having a first widest dimension in the first source/drain region at the first uppermost surface of the first source/drain region in the first cross-sectional view, the conductive feature having a second widest dimension in the first source/drain region below the second uppermost surface of the first source/drain region in the second cross-sectional view. 
 
     
     
       9. The semiconductor structure of  claim 8 , wherein a distance from the second uppermost surface of the first source/drain region to a lowermost surface of the conductive feature in the second cross-sectional view is in a range between 5 nm and 20 nm. 
     
     
       10. The semiconductor structure of  claim 9 , wherein the first source/drain region comprises an epitaxial region, wherein the conductive feature extends into the epitaxial region 10% to 50% of a thickness of the epitaxial region in the second cross-sectional view. 
     
     
       11. The semiconductor structure of  claim 10 , wherein the second widest dimension of the conductive feature is 10% to 50% of a width of the epitaxial region in the second cross-sectional view. 
     
     
       12. The semiconductor structure of  claim 11 , wherein the first widest dimension is in a range from about 14 nm to about 40 nm. 
     
     
       13. The semiconductor structure of  claim 12 , wherein the second widest dimension is in a range from about 15 nm to about 50 nm. 
     
     
       14. The semiconductor structure of  claim 8 , wherein the conductive feature comprises an expanded portion in the first cross-sectional view, wherein the expanded portion extends laterally an amount in a range between 2 nm to 20 nm in both lateral directions in the first cross-sectional view. 
     
     
       15. The semiconductor structure of  claim 8 , wherein the conductive feature contacts a bottom surface of the one or more dielectric layers. 
     
     
       16. A semiconductor structure comprising:
 a semiconductor substrate, the semiconductor substrate comprising a first semiconductor material; 
 an epitaxial region on the semiconductor substrate, the epitaxial region comprising a second semiconductor material; 
 one or more a dielectric layers over the epitaxial region; and 
 a conductive feature extending through the one or more dielectric layers, the conductive feature comprising a first portion and a second portion, the first portion having the one or more dielectric layers along opposing sidewalls, the second portion having a wider width than the first portion, the second portion having an upper surface contacting the epitaxial region in a first cross section, the second portion having a widest width at an uppermost surface of the epitaxial region in a second cross section, the second portion having the epitaxial region along opposing sidewalls in the first cross section. 
 
     
     
       17. The semiconductor structure of  claim 16 , wherein the conductive feature extends lower than an upper surface of the semiconductor substrate. 
     
     
       18. The semiconductor structure of  claim 16 , wherein the conductive feature extends into the epitaxial region to a depth in a range between 10% and 50% of a thickness of the epitaxial region in the first cross section. 
     
     
       19. The semiconductor structure of  claim 16 , wherein the conductive feature comprises a silicide region. 
     
     
       20. The semiconductor structure of  claim 19 , wherein the widest width of the second portion is in a range from 5% to 50% more than a width of the first portion at the upper surface of the epitaxial region.