US12113551B2ActiveUtilityA1

Calibration of anti-aliasing filter mismatch

Assignee: CIRRUS LOGIC INT SEMICONDUCTOR LTDPriority: Aug 25, 2022Filed: Aug 25, 2022Granted: Oct 8, 2024
Est. expiryAug 25, 2042(~16.1 yrs left)· nominal 20-yr term from priority
H03F 3/217H03M 3/458H03M 3/344H03M 3/322H03M 1/1009H03M 3/38H03M 1/06
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16
Claims

Abstract

In accordance with embodiments of the present disclosure, a method may include, in a system comprising a differential filter comprising a plurality of impedance elements, applying a common-mode signal to the differential filter, measuring an output signal of the differential filter in response to the common-mode signal to determine an error due to impedance mismatch of the impedance elements, and tuning one or more of the plurality of impedance elements to minimize the error.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method comprising, in a system comprising a differential filter comprising a plurality of impedance elements:
 applying a common-mode signal to the differential filter; 
 measuring an output signal of the differential filter in response to the common-mode signal to determine an error due to impedance mismatch of the impedance elements; and 
 tuning one or more of the plurality of impedance elements to minimize the error. 
 
     
     
       2. The method of  claim 1 , wherein applying the common-mode signal to the differential filter comprises applying the common-mode signal to inputs of the differential filter. 
     
     
       3. The method of  claim 1 , wherein applying the common-mode signal to the differential filter comprises applying the common-mode signal to common-mode ground nodes of capacitors of the differential filter. 
     
     
       4. The method of  claim 1 , wherein tuning one or more of the plurality of impedance elements comprises tuning one or more capacitances of the differential filter. 
     
     
       5. The method of  claim 1 , wherein tuning one or more of the plurality of impedance elements comprises tuning one or more resistances of the differential filter. 
     
     
       6. The method of  claim 1 , wherein the common-mode signal is greater than one-half of a sampling frequency of an analog-to-digital converter that receives the output signal of the differential filter. 
     
     
       7. The method of  claim 1 , wherein tuning comprises using a closed-loop controller to tune the one or more of the plurality of impedance elements responsive to the error. 
     
     
       8. The method of  claim 1 , wherein measuring an output of the differential filter comprises:
 converting the output signal to a digital equivalent signal; and 
 tuning one or more of the plurality of impedance elements to minimize the digital equivalent signal. 
 
     
     
       9. A system comprising:
 a signal generator configured to apply a common-mode signal to a differential filter comprising a plurality of impedance elements; 
 an error extractor configured to measure an output signal of the differential filter in response to the common-mode signal to determine an error due to impedance mismatch of the impedance elements; and 
 a controller configured to tune one or more of the plurality of impedance elements to minimize the error. 
 
     
     
       10. The system of  claim 9 , wherein applying the common-mode signal to the differential filter comprises applying the common-mode signal to inputs of the differential filter. 
     
     
       11. The system of  claim 9 , wherein applying the common-mode signal to the differential filter comprises applying the common-mode signal to common-mode ground nodes of capacitors of the differential filter. 
     
     
       12. The system of  claim 9 , wherein tuning one or more of the plurality of impedance elements comprises tuning one or more capacitances of the differential filter. 
     
     
       13. The system of  claim 9 , wherein tuning one or more of the plurality of impedance elements comprises tuning one or more resistances of the differential filter. 
     
     
       14. The system of  claim 9 , wherein the common-mode signal is greater than one-half of a sampling frequency of an analog-to-digital converter that receives the output signal of the differential filter. 
     
     
       15. The system of  claim 9 , wherein tuning comprises using a closed-loop controller to tune the one or more of the plurality of impedance elements responsive to the error. 
     
     
       16. The system of  claim 9 , wherein measuring an output of the differential filter comprises:
 converting the output signal to a digital equivalent signal; and 
 tuning one or more of the plurality of impedance elements to minimize the digital equivalent signal.

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