Circuit arrangement with a thermal interface

Abstract

A circuit arrangement has a chip arrangement in the form of an embedded Wafer Level Ball Grid Array (eWLB) arrangement with solder contacts on one side and a thermal interface on a side of the chip arrangement facing away from the solder contacts which is designed to dissipate heat from the semiconductor chip. In examples, the thermal interface has a thermally and electrically conductive material, wherein in a top view of the chip arrangement, a contact area in which the thermally and electrically conductive material is in thermal contact with the chip arrangement is limited to the fan-out area. In examples, the thermal interface has at least one RF absorption layer which is designed to absorb electromagnetic radiation at an operating frequency of the semiconductor chip.

What is claimed is: 
     
       1. A circuit arrangement, comprising:
 a chip arrangement comprising a redistribution layer structure including a first side and a second side arranged opposite to the first side, a semiconductor chip, a potting compound, and solder contacts,
 wherein the semiconductor chip and the potting compound are arranged on the first side of the redistribution layer structure, 
 wherein the semiconductor chip is embedded in the potting compound, 
 wherein the solder contacts are arranged on the second side of the redistribution layer structure, 
 wherein the solder contacts are connected to connections of the semiconductor chip in an electrically conductive manner via conductor structures of the redistribution layer structure, and 
 wherein in a top view of the chip arrangement, at least one of the solder contacts is arranged outside an area that overlaps with the semiconductor chip; and 
 
 a thermal interface on a side of the chip arrangement facing away from the solder contacts that is configured to dissipate heat from the semiconductor chip,
 wherein the thermal interface has a thermally and electrically conductive material, and 
 wherein in the top view of the chip arrangement, a contact area at which the thermally and electrically conductive material is in thermal contact with the chip arrangement is limited to the area that overlaps with the semiconductor chip. 
 
 
     
     
       2. The circuit arrangement as claimed in  claim 1 , further comprising:
 metal parts that are opposite areas of the chip arrangement in which the semiconductor chip is not arranged, on the side facing away from the solder contacts, 
 wherein a distance of the metal parts from the chip arrangement is at least 1.5 mm. 
 
     
     
       3. A circuit arrangement, comprising:
 a chip arrangement comprising:
 a redistribution layer structure including a first side and a second side arranged opposite to the first side, 
 a semiconductor chip, 
 a potting compound, and 
 solder contacts, 
 wherein the semiconductor chip and the potting compound are arranged on the first side of the redistribution layer structure, 
 wherein the semiconductor chip is embedded in the potting compound, 
 wherein the solder contacts are arranged on the second side of the redistribution layer structure, and 
 wherein the solder contacts are connected to connections of the semiconductor chip in an electrically conductive manner via conductor structures of the redistribution layer structure; and 
 
 a thermal interface arranged on a side of the chip arrangement facing away from the solder contacts that is configured to dissipate heat from a rear side of the semiconductor chip,
 wherein the thermal interface has at least one radio-frequency (RF) absorption layer that is configured to absorb electromagnetic radiation at an operating frequency of the semiconductor chip. 
 
 
     
     
       4. The circuit arrangement as claimed in  claim 3 , wherein the thermal interface is arranged on the rear side of the semiconductor chip facing away from the redistribution layer structure and on a side of the potting compound facing away from the redistribution layer structure. 
     
     
       5. The circuit arrangement as claimed in  claim 3 , wherein the at least one RF absorption layer has a material that has a dielectric loss factor tan δ of 0.2 or more at the operating frequency of the semiconductor chip. 
     
     
       6. The circuit arrangement as claimed in  claim 3 , wherein the at least one RF absorption layer has such absorption losses for an electromagnetic radiation leakage emitted as a result of an operation of the semiconductor chip in a direction of the RF absorption layer that, in the case of a total reflection at a side of the thermal interface that is spaced apart from the chip arrangement, a maximum of 10% of this radiation leakage gets back to the chip arrangement. 
     
     
       7. The circuit arrangement as claimed in  claim 3 , wherein the at least one RF absorption layer has a thickness in a range from 0.2 mm to 3 mm. 
     
     
       8. The circuit arrangement as claimed in  claim 3 , wherein the at least one RF absorption layer has a carbon material. 
     
     
       9. The circuit arrangement as claimed in  claim 3 , wherein the at least one RF absorption layer has at least one of: carbon nanotubes, at least one graphene layer, at least one graphite layer, a graphene foam, or a filler made of RF absorbing particles having organometallic carbonyl complexes. 
     
     
       10. The circuit arrangement as claimed in  claim 3 , wherein the at least one RF absorption layer has a material that has a heat conductivity of at least 3 W/(m·K) in a direction away from the chip arrangement. 
     
     
       11. The circuit arrangement as claimed in  claim 3 , wherein the at least one RF absorption layer comprises induction structures that are configured to convert RF radiation from the chip arrangement into eddy currents. 
     
     
       12. The circuit arrangement as claimed in  claim 11 , wherein the induction structures have a grid structure made of an electrically conductive material or a hole pattern in an electrically conductive material. 
     
     
       13. The circuit arrangement as claimed in  claim 3 , wherein the chip arrangement comprises channels that extend from the redistribution layer structure to a surface of the chip arrangement facing away from the redistribution layer structure, wherein the channels are filled with a thermally conductive material. 
     
     
       14. The circuit arrangement as claimed in  claim 3 , wherein the thermal interface has the at least one RF absorption layer and at least one thermally conductive layer,
 wherein the at least one thermally conductive layer has a higher heat conductivity than the at least one RF absorption layer,
 wherein the at least one RF absorption layer has a higher absorption capacity for the electromagnetic radiation at the operating frequency of the semiconductor chip than the at least one thermally conductive layer, and 
 wherein the at least one RF absorption layer is arranged between the chip arrangement and the at least one thermally conductive layer or the at least one thermally conductive layer is arranged between the chip arrangement and the at least one RF absorption layer. 
 
 
     
     
       15. The circuit arrangement as claimed in  claim 14 , wherein the at least one thermally conductive layer has a graphite layer or a graphite laminate. 
     
     
       16. The circuit arrangement as claimed in  claim 14 , wherein the at least one thermally conductive layer has a coating made of a thermally conductive material on the chip arrangement and the at least one RF absorption layer is arranged on the coating made of the thermally conductive material. 
     
     
       17. The circuit arrangement as claimed in  claim 14 , wherein the at least one RF absorption layer has a coating made of an RF absorbing material disposed on the chip arrangement and the at least one thermally conductive layer made of a thermally conductive material and is arranged on the coating made of the RF absorbing material such that the coating made of an RF absorbing material is interposed between the chip arrangement and the at least one thermally conductive layer. 
     
     
       18. The circuit arrangement as claimed in  claim 17 , wherein the coating made of the RF absorbing material has a potting material that is filled with RF absorbing particles, including carbonyl iron powder. 
     
     
       19. The circuit arrangement as claimed in  claim 3 , wherein the thermal interface comprises at least one layer that is compliant and compressible in order to compensate for surface irregularities of the chip arrangement. 
     
     
       20. The circuit arrangement as claimed in  claim 3 , further comprising:
 a stamp made of a thermally and electrically conductive material that is in mechanical contact with a side of the thermal interface facing away from the chip arrangement. 
 
     
     
       21. The circuit arrangement as claimed in  claim 20 , wherein the RF absorption layer has graphene foam,
 wherein a pressure which can be exerted by the stamp on the RF absorption layer is adjustable in order to adjust an absorption frequency of the RF absorption layer. 
 
     
     
       22. The circuit arrangement as claimed in  claim 1 , wherein the thermally and electrically conductive material comprises a first portion having a first lateral dimension that defines the contact area and a second portion that laterally extends from the first portion to define a second lateral dimension that is greater than the first lateral dimension,
 wherein the first portion vertically extends from the contact area to the second portion, and 
 wherein a lateral extension of the second portion hangs over the potting compound outside the area that overlaps with the semiconductor chip to thereby define a gap between the second portion and the potting compound. 
 
     
     
       23. The circuit arrangement as claimed in  claim 22 , wherein the thermally and electrically conductive material has a T-shape in a cross-sectional view thereof. 
     
     
       24. A circuit arrangement, comprising:
 a chip arrangement comprising a redistribution layer structure including a first side and a second side arranged opposite to the first side, a semiconductor chip, a potting compound, and solder contacts,
 wherein the semiconductor chip and the potting compound are arranged on the first side of the redistribution layer structure, 
 wherein the semiconductor chip is embedded in the potting compound, 
 wherein the solder contacts are arranged on the second side of the redistribution layer structure, and 
 wherein in a top view of the chip arrangement, at least one of the solder contacts is arranged outside an area that overlaps with the semiconductor chip; and 
 
 a thermally and electrically conductive material on a side of the chip arrangement facing away from the solder contacts,
 wherein, in the top view of the chip arrangement, a contact area at which the thermally and electrically conductive material is in thermal contact with the chip arrangement is limited to the area that overlaps with the semiconductor chip. 
 
 
     
     
       25. The circuit arrangement as claimed in  claim 24 , further comprising:
 metal parts that are opposite areas of the chip arrangement in which the semiconductor chip is not arranged, on the side facing away from the solder contacts. 
 
     
     
       26. The circuit arrangement as claimed in  claim 25 , wherein a distance of the metal parts from the chip arrangement is at least 1.5 mm. 
     
     
       27. The circuit arrangement as claimed in  claim 23 , further comprising:
 a thermal interface that includes the thermally and electrically conductive material,
 wherein the thermal interface has at least one radio-frequency (RF) absorption layer that is configured to absorb electromagnetic radiation at an operating frequency of the semiconductor chip.