US12100366B2ActiveUtilityA1

Semiconductor device

83
Assignee: SEMICONDUCTOR ENERGY LABPriority: Sep 9, 2010Filed: Jun 22, 2023Granted: Sep 24, 2024
Est. expirySep 9, 2030(~4.1 yrs left)· nominal 20-yr term from priority
Inventors:Hajime KimuraAtsushi Umezaki
G09G 2310/0286G09G 2310/08G09G 2320/043G09G 3/3688G09G 3/3677G09G 2320/0209G09G 2300/0426G09G 2300/0814G09G 2300/0819G09G 2320/0223G09G 3/2096G09G 3/3648
83
PatentIndex Score
0
Cited by
166
References
18
Claims

Abstract

A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A display device comprising:
 a first gate driver circuit; 
 a second gate driver circuit; and 
 a pixel portion between the first gate driver circuit and the second gate driver circuit, 
 wherein each of the first gate driver circuit and the second gate driver circuit comprises first to eleventh transistors, 
 wherein in each of the first gate driver circuit and the second gate driver circuit, 
 one of a source and a drain of the first transistor is electrically connected to a gate line; 
 one of a source and a drain of the second transistor is electrically connected to the gate line; 
 the other of the source and the drain of the second transistor is configured to be supplied with a power supply potential; 
 one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor; 
 a gate of the third transistor is electrically connected to a gate of the first transistor; 
 one of a source and a drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor; 
 a gate of the fourth transistor is electrically connected to a gate of the second transistor; 
 one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor; 
 one of a source and a drain of the sixth transistor is electrically connected to the gate of the first transistor; 
 one of a source and a drain of the seventh transistor is electrically connected to the gate of the second transistor; 
 the other of the source and the drain of the seventh transistor is electrically connected to a gate of the seventh transistor; 
 one of a source and a drain of the eighth transistor is electrically connected to the gate of the second transistor; 
 one of a source and a drain of the ninth transistor is electrically connected to a gate of the sixth transistor; 
 the other of the source and the drain of the ninth transistor is electrically connected to a gate of the ninth transistor; 
 one of a source and a drain of the tenth transistor is electrically connected to the gate of the sixth transistor; 
 a gate of the tenth transistor is electrically connected to a gate of the eighth transistor; 
 one of a source and a drain of the eleventh transistor is electrically connected to the gate of the first transistor; and 
 wherein in the first gate driver circuit, 
 the other of the source and the drain of the first transistor is electrically connected to a first wiring; 
 the one of the source and the drain of the third transistor is electrically connected to the first wiring; 
 the other of the source and the drain of the third transistor is electrically connected to a third wiring; 
 the other of the source and the drain of the fourth transistor is electrically connected to a second wiring; 
 the other of the source and the drain of the fifth transistor is electrically connected to a fourth wiring; 
 the other of the source and the drain of the sixth transistor is electrically connected to the second wiring; 
 the other of the source and the drain of the seventh transistor is electrically connected to a fifth wiring; 
 the other of the source and the drain of the eighth transistor is electrically connected to the second wiring; 
 the other of the source and the drain of the ninth transistor is electrically connected to a sixth wiring; 
 the other of the source and the drain of the tenth transistor is electrically connected to the second wiring; 
 the other of the source and the drain of the eleventh transistor is electrically connected to the second wiring; and 
 a gate of the eleventh transistor is electrically connected to a seventh wiring, 
 wherein in the second gate driver circuit, 
 the other of the source and the drain of the first transistor is electrically connected to an eighth wiring; 
 the one of the source and the drain of the third transistor is electrically connected to the eighth wiring; 
 the other of the source and the drain of the third transistor is electrically connected to a tenth wiring; 
 the other of the source and the drain of the fourth transistor is electrically connected to a ninth wiring; 
 the other of the source and the drain of the fifth transistor is electrically connected to an eleventh wiring; 
 the other of the source and the drain of the sixth transistor is electrically connected to the ninth wiring; 
 the other of the source and the drain of the seventh transistor is electrically connected to a twelfth wiring; 
 the other of the source and the drain of the eighth transistor is electrically connected to the ninth wiring; 
 the other of the source and the drain of the ninth transistor is electrically connected to a thirteenth wiring; 
 the other of the source and the drain of the tenth transistor is electrically connected to the ninth wiring; 
 the other of the source and the drain of the eleventh transistor is electrically connected to the ninth wiring; and 
 a gate of the eleventh transistor is electrically connected to a fourteenth wiring, 
 wherein in each of the first gate driver circuit and the second gate driver circuit, a channel width of the first transistor is larger than a channel width of the second transistor, and 
 wherein each of the second wiring and the ninth wiring is configured to be supplied with the power supply potential. 
 
     
     
       2. The display device according to  claim 1 ,
 wherein in the first gate driver circuit, the fifth transistor is configured to control a timing of supplying a potential of the fourth wiring to the gate of the first transistor, and 
 wherein in the second gate driver circuit, the fifth transistor is configured to control a timing of supplying a potential of the eleventh wiring to the gate of the first transistor. 
 
     
     
       3. The display device according to  claim 1 , wherein in each of the first gate driver circuit and the second gate driver circuit, the eighth transistor is configured to control a timing of supplying the power supply potential to the gate of the second transistor. 
     
     
       4. The display device according to  claim 1 , wherein in each of the first gate driver circuit and the second gate driver circuit, the tenth transistor is configured to control a timing of supplying the power supply potential to the gate of the sixth transistor. 
     
     
       5. The display device according to  claim 1 , wherein the first wiring is electrically connected to the eighth wiring. 
     
     
       6. The display device according to  claim 1 , wherein the second wiring is electrically connected to the ninth wiring. 
     
     
       7. A display device comprising:
 a first gate driver circuit; 
 a second gate driver circuit; and 
 a pixel portion between the first gate driver circuit and the second gate driver circuit, 
 wherein each of the first gate driver circuit and the second gate driver circuit comprises first to eleventh transistors, 
 wherein in each of the first gate driver circuit and the second gate driver circuit, 
 one of a source and a drain of the first transistor is electrically connected to a gate line; 
 one of a source and a drain of the second transistor is electrically connected to the gate line; 
 the other of the source and the drain of the second transistor is configured to be supplied with a power supply potential; 
 one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor; 
 a gate of the third transistor is electrically connected to a gate of the first transistor; 
 one of a source and a drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor; 
 a gate of the fourth transistor is electrically connected to a gate of the second transistor; 
 one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor; 
 one of a source and a drain of the sixth transistor is electrically connected to the gate of the first transistor; 
 one of a source and a drain of the seventh transistor is electrically connected to the gate of the second transistor; 
 the other of the source and the drain of the seventh transistor is electrically connected to a gate of the seventh transistor; 
 one of a source and a drain of the eighth transistor is electrically connected to the gate of the second transistor; 
 one of a source and a drain of the ninth transistor is electrically connected to a gate of the sixth transistor; 
 the other of the source and the drain of the ninth transistor is electrically connected to a gate of the ninth transistor; 
 one of a source and a drain of the tenth transistor is electrically connected to the gate of the sixth transistor; 
 a gate of the tenth transistor is electrically connected to a gate of the eighth transistor; 
 one of a source and a drain of the eleventh transistor is electrically connected to the gate of the first transistor; and 
 wherein in the first gate driver circuit, 
 the other of the source and the drain of the first transistor is electrically connected to a first wiring; 
 the other of the source and the drain of the second transistor is electrically connected to a second wiring; 
 the one of the source and the drain of the third transistor is electrically connected to the first wiring; 
 the other of the source and the drain of the third transistor is electrically connected to a third wiring; 
 the other of the source and the drain of the fourth transistor is electrically connected to a second wiring; 
 the other of the source and the drain of the fifth transistor is electrically connected to a fourth wiring; 
 the other of the source and the drain of the sixth transistor is electrically connected to the second wiring; 
 the other of the source and the drain of the seventh transistor is electrically connected to a fifth wiring; 
 the other of the source and the drain of the eighth transistor is electrically connected to the second wiring; 
 the other of the source and the drain of the ninth transistor is electrically connected to a sixth wiring; 
 the other of the source and the drain of the tenth transistor is electrically connected to the second wiring; 
 the other of the source and the drain of the eleventh transistor is electrically connected to the second wiring; and 
 a gate of the eleventh transistor is electrically connected to a seventh wiring, 
 wherein in the second gate driver circuit, 
 the other of the source and the drain of the first transistor is electrically connected to an eighth wiring; 
 the one of the source and the drain of the third transistor is electrically connected to the eighth wiring; 
 the other of the source and the drain of the third transistor is electrically connected to a tenth wiring; 
 the other of the source and the drain of the fourth transistor is electrically connected to a ninth wiring; 
 the other of the source and the drain of the fifth transistor is electrically connected to an eleventh wiring; 
 the other of the source and the drain of the sixth transistor is electrically connected to the ninth wiring; 
 the other of the source and the drain of the seventh transistor is electrically connected to a twelfth wiring; 
 the other of the source and the drain of the eighth transistor is electrically connected to the ninth wiring; 
 the other of the source and the drain of the ninth transistor is electrically connected to a thirteenth wiring; 
 the other of the source and the drain of the tenth transistor is electrically connected to the ninth wiring; 
 the other of the source and the drain of the eleventh transistor is electrically connected to the ninth wiring; and 
 a gate of the eleventh transistor is electrically connected to a fourteenth wiring, 
 wherein in each of the first gate driver circuit and the second gate driver circuit, a channel width of the first transistor is larger than a channel width of the second transistor, 
 wherein each of the second wiring and the ninth wiring is configured to be supplied with the power supply potential, and 
 wherein the first wiring is configured to be supplied with a clock signal. 
 
     
     
       8. The display device according to  claim 7 , wherein the second wiring is electrically connected to the ninth wiring. 
     
     
       9. The display device according to  claim 8 ,
 wherein in the first gate driver circuit, the fifth transistor is configured to control a timing of supplying a potential of the fourth wiring to the gate of the first transistor, and 
 wherein in the second gate driver circuit, the fifth transistor is configured to control a timing of supplying a potential of the eleventh wiring to the gate of the first transistor. 
 
     
     
       10. The display device according to  claim 8 , wherein in each of the first gate driver circuit and the second gate driver circuit, the eighth transistor is configured to control a timing of supplying the power supply potential to the gate of the second transistor. 
     
     
       11. The display device according to  claim 8 , wherein in each of the first gate driver circuit and the second gate driver circuit, the tenth transistor is configured to control a timing of supplying the power supply potential to the gate of the sixth transistor. 
     
     
       12. The display device according to  claim 7 , wherein the first wiring is electrically connected to the eighth wiring. 
     
     
       13. A display device comprising:
 a first gate driver circuit; 
 a second gate driver circuit; and 
 a pixel portion between the first gate driver circuit and the second gate driver circuit, 
 wherein each of the first gate driver circuit and the second gate driver circuit comprises first to eleventh transistors, 
 wherein in each of the first gate driver circuit and the second gate driver circuit, 
 one of a source and a drain of the first transistor is electrically connected to a gate line; 
 one of a source and a drain of the second transistor is electrically connected to the gate line; 
 the other of the source and the drain of the second transistor is configured to be supplied with a power supply potential; 
 one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor; 
 a gate of the third transistor is electrically connected to a gate of the first transistor; 
 one of a source and a drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor; 
 a gate of the fourth transistor is electrically connected to a gate of the second transistor; 
 one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor; 
 one of a source and a drain of the sixth transistor is electrically connected to the gate of the first transistor; 
 one of a source and a drain of the seventh transistor is electrically connected to the gate of the second transistor; 
 the other of the source and the drain of the seventh transistor is electrically connected to a gate of the seventh transistor; 
 one of a source and a drain of the eighth transistor is electrically connected to the gate of the second transistor; 
 one of a source and a drain of the ninth transistor is electrically connected to a gate of the sixth transistor; 
 the other of the source and the drain of the ninth transistor is electrically connected to a gate of the ninth transistor; 
 one of a source and a drain of the tenth transistor is electrically connected to the gate of the sixth transistor; 
 a gate of the tenth transistor is electrically connected to a gate of the eighth transistor; 
 one of a source and a drain of the eleventh transistor is electrically connected to the gate of the first transistor; and 
 wherein in the first gate driver circuit, 
 the other of the source and the drain of the first transistor is electrically connected to a first wiring; 
 the one of the source and the drain of the third transistor is electrically connected to the first wiring; 
 the other of the source and the drain of the third transistor is electrically connected to a third wiring; 
 the other of the source and the drain of the fourth transistor is electrically connected to a second wiring; 
 the other of the source and the drain of the fifth transistor is electrically connected to a fourth wiring; 
 the other of the source and the drain of the sixth transistor is electrically connected to the second wiring; 
 the other of the source and the drain of the seventh transistor is electrically connected to a fifth wiring; 
 the other of the source and the drain of the eighth transistor is electrically connected to the second wiring; 
 the other of the source and the drain of the ninth transistor is electrically connected to a sixth wiring; 
 the other of the source and the drain of the tenth transistor is electrically connected to the second wiring; 
 the other of the source and the drain of the eleventh transistor is electrically connected to the second wiring; and 
 a gate of the eleventh transistor is electrically connected to a seventh wiring, 
 wherein in the second gate driver circuit, 
 the other of the source and the drain of the first transistor is electrically connected to an eighth wiring; 
 the one of the source and the drain of the third transistor is electrically connected to the eighth wiring; 
 the other of the source and the drain of the third transistor is electrically connected to a tenth wiring; 
 the other of the source and the drain of the fourth transistor is electrically connected to a ninth wiring; 
 the other of the source and the drain of the fifth transistor is electrically connected to an eleventh wiring; 
 the other of the source and the drain of the sixth transistor is electrically connected to the ninth wiring; 
 the other of the source and the drain of the seventh transistor is electrically connected to a twelfth wiring; 
 the other of the source and the drain of the eighth transistor is electrically connected to the ninth wiring; 
 the other of the source and the drain of the ninth transistor is electrically connected to a thirteenth wiring; 
 the other of the source and the drain of the tenth transistor is electrically connected to the ninth wiring; 
 the other of the source and the drain of the eleventh transistor is electrically connected to the ninth wiring; and 
 a gate of the eleventh transistor is electrically connected to a fourteenth wiring, 
 wherein in each of the first gate driver circuit and the second gate driver circuit, a channel width of the first transistor is larger than a channel width of the second transistor, 
 wherein each of the second wiring and the ninth wiring is configured to be supplied with the power supply potential, and 
 wherein the third wiring is configured to output a first signal. 
 
     
     
       14. The display device according to  claim 13 ,
 wherein in the first gate driver circuit, the fifth transistor is configured to control a timing of supplying a potential of the fourth wiring to the gate of the first transistor, and 
 wherein in the second gate driver circuit, the fifth transistor is configured to control a timing of supplying a potential of the eleventh wiring to the gate of the first transistor. 
 
     
     
       15. The display device according to  claim 13 , wherein in each of the first gate driver circuit and the second gate driver circuit, the eighth transistor is configured to control a timing of supplying the power supply potential to the gate of the second transistor. 
     
     
       16. The display device according to  claim 13 , wherein in each of the first gate driver circuit and the second gate driver circuit, the tenth transistor is configured to control a timing of supplying the power supply potential to the gate of the sixth transistor. 
     
     
       17. The display device according to  claim 13 , wherein the first wiring is electrically connected to the eighth wiring. 
     
     
       18. The display device according to  claim 13 , wherein the second wiring is electrically connected to the ninth wiring.

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