US12074199B2ActiveUtilityA1

Semiconductor device with a field plate extending from drain

Assignee: INNOSCIENCE ZHUHAI TECHNOLOGY CO LTDPriority: Mar 23, 2020Filed: Oct 12, 2022Granted: Aug 27, 2024
Est. expiryMar 23, 2040(~13.7 yrs left)· nominal 20-yr term from priority
H10D 62/8503H10D 62/82H10D 99/00H10D 84/83H10D 64/112H10D 64/111H10D 30/015H10D 64/251H10D 62/343H10D 62/116H10D 62/106H10D 62/10H10D 84/811H10D 30/4732H10D 62/221H10D 62/151H10D 30/475H01L 29/267H01L 29/2003H01L 29/66969H01L 29/66462H01L 29/404H01L 29/402H01L 27/088H01L 29/0847
72
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Cited by
12
References
20
Claims

Abstract

Some embodiments of the present disclosure provide a semiconductor device including a channel layer, a barrier layer, a p-type doped III-V layer, a gate, a drain, and a doped semiconductor layer. The barrier layer is disposed on the channel layer. The p-type doped III-V layer is disposed on the barrier layer. The gate is disposed on the p-type doped III-V layer. The drain is disposed on the barrier layer. The doped semiconductor layer is disposed on the barrier layer and is covered by the drain. The drain has a first portion located between the p-type doped III-V layer and an entirety of the doped semiconductor layer.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A semiconductor device, comprising:
 a channel layer; 
 a barrier layer disposed on the channel layer; 
 a p-type doped III-V layer disposed on the barrier layer; 
 a gate disposed on the p-type doped III-V layer; 
 a drain disposed on the barrier layer; and 
 a doped semiconductor layer disposed on the barrier layer and covered by the drain, wherein the drain has a first portion located between the p-type doped III-V layer and an entirety of the doped semiconductor layer; 
 wherein the semiconductor device further comprises a field plate extending from the drain toward the gate; the field plate is provided with a lower surface higher than an upper surface of the gate. 
 
     
     
       2. The semiconductor device according to  claim 1 , wherein the first portion of the drain is in contact with the barrier layer. 
     
     
       3. The semiconductor device according to  claim 1 , wherein the drain has a second portion, and the entirety of the doped semiconductor layer is located between the first and second portions of the drain. 
     
     
       4. The semiconductor device according to  claim 3 , wherein the second portion of the drain is in contact with the barrier layer. 
     
     
       5. The semiconductor device according to  claim 1 , wherein the doped semiconductor layer has a side surface facing away from the gate and free from coverage of the drain. 
     
     
       6. The semiconductor device according to  claim 1 , wherein the doped semiconductor layer has a side surface facing the gate, and the drain extends from the side surface of the doped semiconductor layer to a top surface of the doped semiconductor layer. 
     
     
       7. The semiconductor device according to  claim 1 , wherein the doped semiconductor layer is narrower than the drain. 
     
     
       8. The semiconductor device according to  claim 1 , wherein the field plate is connected to the drain. 
     
     
       9. The semiconductor device according to  claim 8 , wherein an entirety of the field plate is at a position higher than the doped semiconductor layer. 
     
     
       10. The semiconductor device according to  claim 1 , wherein materials of the doped semiconductor layer and the p-type doped III-V layer are different. 
     
     
       11. A semiconductor device, comprising:
 a channel layer; 
 a barrier layer disposed on the channel layer; 
 a first gate and a second gate disposed on the barrier layer; 
 a drain disposed between the first gate and the second gate; and 
 a doped semiconductor layer disposed on the barrier layer and covered by the drain, wherein the drain has a first portion located between the first gate and an entirety of the doped semiconductor layer; 
 wherein the semiconductor device further comprises a field plate extending from the drain toward the first gate; the field plate is provided with a lower surface higher than an upper surface of the first gate. 
 
     
     
       12. The semiconductor device according to  claim 11 , wherein the first portion of the drain is in contact with the barrier layer. 
     
     
       13. The semiconductor device according to  claim 11 , wherein the drain has a second portion located between the second gate and the entirety of the doped semiconductor layer. 
     
     
       14. The semiconductor device according to  claim 13 , wherein the second portion of the drain is in contact with the barrier layer. 
     
     
       15. The semiconductor device according to  claim 11 , wherein the doped semiconductor layer has a side surface facing away from the first gate and covered by the drain. 
     
     
       16. The semiconductor device according to  claim 11 , wherein the doped semiconductor layer has a first side surface facing the first gate, and the drain extends from the first side surface of the doped semiconductor layer to a top surface of the doped semiconductor layer. 
     
     
       17. The semiconductor device according to  claim 16 , wherein the doped semiconductor layer has a second side surface facing the second gate, and the drain extends from the second side surface of the doped semiconductor layer to the top surface of the doped semiconductor layer. 
     
     
       18. The semiconductor device according to  claim 11 , wherein the doped semiconductor layer is narrower than the drain. 
     
     
       19. The semiconductor device according to  claim 11 , wherein the field plate is connected to the drain. 
     
     
       20. The semiconductor device according to  claim 19 , wherein an entirety of the field plate is at a position higher than the doped semiconductor layer.

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