Analog-to-digital conversion circuit and method having speed-up comparison mechanism

Abstract

The present invention discloses an analog-to-digital conversion circuit having speed-up comparison mechanism. Each of a positive and a negative capacitor arrays receives a positive and a negative input voltages to generate a positive and a negative output voltages. A first comparator performs comparison thereon to generate a first comparison result and a second comparator performs comparison according to a reference voltage to generate a second comparison result. A control circuit switches a capacitor enabling combination of the capacitor arrays according to the first comparison result and outputs a digital code as a digital output signal when the positive and the negative output voltages equal. The control circuit operates in a speed-up switching mode when a difference between the positive and the negative output voltages is outside of a predetermined range defined by the reference voltage and operates in a normal switching mode when the difference is within the predetermined range.

What is claimed is: 
     
       1. An analog-to-digital conversion circuit having speed-up comparison mechanism, comprising:
 a positive capacitor array configured to receive a positive input voltage and output a positive output voltage; 
 a negative capacitor array configured to receive a negative input voltage and output a negative output voltage; 
 a first comparator configured to compare the positive output voltage and the negative output voltage to generate a first comparison result; 
 a second comparator configured to compare the positive output voltage and the negative output voltage according to a reference voltage to generate a second comparison result; and 
 a control circuit configured to receive the first comparison result and the second comparison result; 
 wherein the control circuit switches a capacitor enabling combination of the positive capacitor array and the negative capacitor array according to the first comparison result by using a digital code in each of a plurality of switching stages, and outputs the corresponding digital code as a digital output signal when the positive output voltage and the negative output voltage equal to each other; 
 the control circuit, according to the second comparison result, operates in a speed-up switching mode when a difference between the positive output voltage and the negative output voltage is beyond a predetermined range defined by the reference voltage to control the positive capacitor array and the negative capacitor array to switch according to a first capacitor switching speed, and operates in a normal switching mode when the difference is within the predetermined range to control the positive capacitor array and the negative capacitor array to switch according to a second capacitor switching speed, the first capacitor switching speed being larger than the second capacitor switching speed. 
 
     
     
       2. The analog-to-digital conversion circuit of  claim 1 , wherein the second comparator comprises:
 a positive comparator configured to compare the positive output voltage and the reference voltage to generate a positive comparison result comprised by the second comparison result; and 
 a negative comparator configured to compare the negative output voltage and the reference voltage to generate a negative comparison result comprised by the second comparison result; 
 wherein the control circuit is configured to set a range between a positive value and a negative value of the reference voltage as the predetermined range, and determine whether the difference between the positive output voltage and the negative output voltage is within the predetermined range according to the second comparison result. 
 
     
     
       3. The analog-to-digital conversion circuit of  claim 2 , wherein the reference voltage is 100 millivolts (mV). 
     
     
       4. The analog-to-digital conversion circuit of  claim 1 , wherein each of the positive capacitor array and the negative capacitor array comprises:
 a plurality of capacitors; 
 a capacitor switching circuit electrically coupled to the capacitors and configured to switch and enable the corresponding capacitors according to the digital code; and 
 a plurality of speed-up switching circuits each electrically coupled to a group of corresponding capacitors of the capacitors and configured to simultaneously enable the group of corresponding capacitors according to a speed-up switching signal; 
 wherein the control circuit, operating in the speed-up switching mode and in each of the switching stages, enables a target capacitor of the capacitors through the capacitor switching circuit according to the digital code, and simultaneously enables the corresponding capacitors that corresponds to the target capacitor through the speed-up switching circuits according to the speed-up switching signal; 
 the control circuit, operating in the normal switching mode and in each of the switching stages, only enables the target capacitor of the capacitors through the capacitor switching circuit according to the digital code. 
 
     
     
       5. The analog-to-digital conversion circuit of  claim 1 , wherein each of the positive capacitor array and the negative capacitor array comprises:
 a plurality of capacitors; 
 a capacitor switching circuit electrically coupled to the capacitors and configured to switch and enable the corresponding capacitors according to the digital code; and 
 a plurality of delay circuits each electrically coupled to neighboring two of the capacitors, each comprising a plurality of delay units to determine a switching time of the neighboring two of the capacitors, and each configured to bypass at least a part of the delay units according to a speed-up switching signal; 
 wherein the control circuit, operating in the speed-up switching mode and in each of the switching stages, enables a target capacitor of the capacitors through the capacitor switching circuit according to the digital code, and bypasses at least one of the delay units of one of the delay circuits between the target capacitor and a next capacitor according to the speed-up switching signal; 
 the control circuit, operating in the normal switching mode and in each of the switching stages, only enables the target capacitor of the capacitors through the capacitor switching circuit according to the digital code. 
 
     
     
       6. An analog-to-digital conversion method having speed-up comparison mechanism, comprising:
 receiving a positive input voltage and outputting a positive output voltage by a positive capacitor array; 
 receiving a negative input voltage and outputting a negative output voltage by a negative capacitor array; 
 comparing the positive output voltage and the negative output voltage to generate a first comparison result by a first comparator; 
 comparing the positive output voltage and the negative output voltage according to a reference voltage to generate a second comparison result by a second comparator; 
 receiving the first comparison result by a control circuit to switch a capacitor enabling combination of the positive capacitor array and the negative capacitor array according to the first comparison result by using a digital code in each of a plurality of switching stages, and output the corresponding digital code as a digital output signal when the positive output voltage and the negative output voltage equal to each other; and 
 receiving the second comparison result by the control circuit to, according to the second comparison result, operate in a speed-up switching mode when a difference between the positive output voltage and the negative output voltage is beyond a predetermined range defined by the reference voltage to control the positive capacitor array and the negative capacitor array to switch according to a first capacitor switching speed, and operate in a normal switching mode when the difference is within the predetermined range to control the positive capacitor array and the negative capacitor array to switch according to a second capacitor switching speed, the first capacitor switching speed being larger than the second capacitor switching speed. 
 
     
     
       7. The analog-to-digital conversion method of  claim 6 , further comprising:
 comparing the positive output voltage and the reference voltage to generate a positive comparison result comprised by the second comparison result by a positive comparator comprised by the second comparator; 
 comparing the negative output voltage and the reference voltage to generate a negative comparison result comprised by the second comparison result by a negative comparator comprised by the second comparator; and 
 setting a range between a positive value and a negative value of the reference voltage as the predetermined range, and determining whether the difference between the positive output voltage and the negative output voltage is within the predetermined range by the control circuit according to the second comparison result. 
 
     
     
       8. The analog-to-digital conversion method of  claim 7 , wherein the reference voltage is 100 millivolts. 
     
     
       9. The analog-to-digital conversion method of  claim 6 , wherein each of the positive capacitor array and the negative capacitor array comprises a plurality of capacitors, a capacitor switching circuit and a plurality of speed-up switching circuits, the capacitor switching circuit electrically coupled to the capacitors and configured to switch and enable the corresponding capacitors according to the digital code, and the speed-up switching circuits each electrically coupled to a group of corresponding capacitors of the capacitors and configured to simultaneously enable the group of corresponding capacitors according to a speed-up switching signal, wherein the analog-to-digital conversion method further comprises:
 operating the control circuit in the speed-up switching mode and in each of the switching stages, to enable a target capacitor of the capacitors through the capacitor switching circuit according to the digital code, and to simultaneously enable the corresponding capacitors that corresponds to the target capacitor through the speed-up switching circuits according to the speed-up switching signal; 
 operating the control circuit in the normal switching mode and in each of the switching stages, to only enable the target capacitor of the capacitors through the capacitor switching circuit according to the digital code. 
 
     
     
       10. The analog-to-digital conversion method of  claim 6 , wherein each of the positive capacitor array and the negative capacitor array comprises a plurality of capacitors, a capacitor switching circuit and a plurality of delay circuits, the capacitor switching circuit electrically coupled to the capacitors and configured to switch and enable the corresponding capacitors according to the digital code, and the delay circuits each electrically coupled to neighboring two of the capacitors, each comprising a plurality of delay units to determine a switching time of neighboring two of the capacitors, and each configured to bypass at least a part of the delay units according to a speed-up switching signal, wherein the analog-to-digital conversion method further comprises:
 operating the control circuit in the speed-up switching mode and in each of the switching stages, enables a target capacitor of the capacitors through the capacitor switching circuit according to the digital code, and bypasses at least one of the delay units of one of the delay circuits between the target capacitor and a next capacitor according to the speed-up switching signal; 
 operating the control circuit in the normal switching mode and in each of the switching stages, only enables the target capacitor of the capacitors through the capacitor switching circuit according to the digital code.