Quasi-adiabatic logic circuits

Abstract

Apparatus and associated methods relate to quasi-adiabatic logic gates in which at least one supply terminal receives a periodic power signal. The quasi-adiabatic logic gate is configured to perform a specific logic function operative upon one or more input signals. When the quasi-adiabatic logic gate switches the output from one logic state to another logic state, the transient switching portion of the output signal substantially tracks the periodic supply signal. Such a periodic supply signal can be one that transitions gradually between low and high voltage levels. Such periodic supply signals results in a transient switching portion of the logic signal having lower frequency components than have traditional CMOS logic gate transients. The quasi-adiabatic logic gate has a periodic clock signal that is not in phase with the periodic power signal.

The invention claimed is: 
     
       1. A quasi-adiabatic logic gate comprising:
 first and second clock input terminals configured to receive complementary first and second periodic clock signals, respectively; 
 one or more logic input terminals configured to receive one or more corresponding logic input signals; 
 a logic output terminal configured to output a logic output signal; 
 a pullup network including one or more pullup transistors configured to perform a pullup logic function, each of the one or more pullup transistors of the pullup network having a control node coupled to a corresponding one of the logic input terminals, the pullup network configured to modulate conductivity between a first supply node and an intermediate pullup node based on the pullup logic function that the pullup network is configured to perform and the logic input signals received on the logic input terminals; 
 a pulldown network including one or more pulldown transistors configured to perform a pulldown logic function that is the complement of the pullup logic function performed by the pullup network, each of the one or more pulldown transistors of the pulldown network having a control node coupled to a corresponding one of the logic input terminals, the pulldown network configured to modulate conductivity between a second supply node and an intermediate pulldown node based on the pulldown logic function that the pulldown network is configured to perform and the logic input signals received on the logic input terminals; 
 a pullup clocking transistor having a pullup control node coupled to the first clock terminal, the pullup clocking transistor having a control node coupled to the first clock input terminal, the pullup clocking transistor configured to modulate conductivity, based on the first periodic clock signal received on the first clock terminal, between the intermediate pullup node and a logic output terminal; 
 a pulldown clocking transistor having a pulldown control node coupled to the second clock terminal, the pulldown clocking transistor having a control node coupled to the second clock input terminal, the pulldown clocking transistor configured to modulate conductivity, based on the second periodic clock signal received on the second clock terminal, between the intermediate pulldown node and a logic output terminal; 
 wherein the first supply node is periodically driven by a first supply signal in a lagging phase relation with the second periodic clock signal, and wherein the second supply node is periodically driven by a second supply signal in a lagging phase relation with and the first clock signal. 
 
     
     
       2. The quasi-adiabatic logic gate of  claim 1 , wherein the phase relation between the first supply signal and the second clock signal is one in which the second clock signal leads the first supply signal by between 2% and 50% of a period of the periodically driven first supply signal. 
     
     
       3. The quasi-adiabatic logic gate of  claim 2 , wherein the phase relation between the first supply signal and the second clock signal is one in which the second clock signal leads the first supply signal by between 5% and 20% of a period of the periodically driven first supply signal. 
     
     
       4. The quasi-adiabatic logic gate of  claim 1 , wherein the phase relation between the second supply signal and the first clock signal is one in which the first clock signal leads the second supply signal by between 2% and 50% of a period of the periodically driven second supply signal. 
     
     
       5. The quasi-adiabatic logic gate of  claim 4 , wherein the phase relation between the second supply signal and the first clock signal is one in which the first clock signal leads the second supply signal by between 5% and 20% of a period of the periodically driven second supply signal. 
     
     
       6. The quasi-adiabatic logic gate of  claim 4 , wherein a difference between the first and second DC voltages is greater than two times a threshold voltage of the pullup transistors. 
     
     
       7. The quasi-adiabatic logic gate of  claim 6 , wherein a difference between the first and second DC voltages is greater than five times a threshold voltage of the pullup transistors. 
     
     
       8. The quasi-adiabatic logic gate of  claim 4 , wherein a difference between the first and second DC voltages is greater than two times a threshold voltage of the pulldown transistors. 
     
     
       9. The quasi-adiabatic logic gate of  claim 4 , wherein a difference between the first and second DC voltages is greater than five times a threshold voltage of the pulldown transistors. 
     
     
       10. The quasi-adiabatic logic gate of  claim 1 , wherein the first supply signal driving the first supply node oscillates between a first DC voltage and a second DC voltage, and wherein the second supply signal driving the second supply node oscillates between the second DC voltage and the first DC voltage. 
     
     
       11. The quasi-adiabatic logic gate of  claim 10 , wherein the pullup transistors and the pullup clocking transistors comprise PMOS transistors, each having a body node driven by a DC voltage above the first DC voltage. 
     
     
       12. The quasi-adiabatic logic gate of  claim 10 , wherein the pullup transistors and the pullup clocking transistors comprise PMOS transistors, each having a body node driven by a periodic signal having a voltage above a voltage of the first supply signal. 
     
     
       13. The quasi-adiabatic logic gate of  claim 10  wherein the pulldown transistors and the pulldown clocking transistors comprise NMOS transistors, each having a body node driven by a DC voltage below the second DC voltage. 
     
     
       14. The quasi-adiabatic logic of  claim 10 , wherein the pulldown transistors and the pulldown clocking transistors comprise NMOS transistors, each having a body node driven by a periodic signal having a voltage below a voltage of the second supply signal. 
     
     
       15. The quasi-adiabatic logic gate of  claim 1 , wherein the first supply signal driving the first supply node oscillates between a first DC voltage and an intermediate DC voltage between the first and a second DC voltages, and wherein the second supply signal driving a second supply node oscillates between the second DC voltage and the intermediate DC voltage. 
     
     
       16. The quasi-adiabatic logic gate of  claim 15 , wherein the first and second supply signals are complementary sinusoidal signals. 
     
     
       17. The quasi-adiabatic logic gate of  claim 1 , wherein complementary first and second periodic clock signals are complementary sinusoidal signals. 
     
     
       18. The quasi-adiabatic logic gate of  claim 1 , further comprising
 a clock generator having first and second output nodes, the clock generator configured to provide the first sinusoidal clock signal at the first output node and the second sinusoidal clock signal at the and second output node. 
 
     
     
       19. The quasi-adiabatic logic gate of  claim 1 , further comprising:
 an inductor coupled between the first output node of the clock generator and the first supply node. 
 
     
     
       20. The quasi-adiabatic logic gate of  claim 19 , wherein the inductor is a first inductor, the quasi-adiabatic CMOS logic gate further comprising:
 a second inductor coupled between the second output node of the clock generator and the second supply node.