System and method for double data rate (DDR) chip-kill recovery

Abstract

A system and method for double data rate (DDR) chip-kill decoding using an array of ECC erasure decoders operating in parallel to identify a location of a chip-kill event associated with a DDR memory device. The ECC erasure decoder that correctly identifies the chip-kill location is then used to decode subsequent DDR bursts transmitted from the DDR memory device.

What is claimed is: 
     
       1. A method for double data rate (DDR) chip-kill decoding, the method comprising:
 receiving, at a DDR interface, a DDR burst comprising a plurality of encoded symbols from a DDR memory device, wherein the DDR memory device comprises a plurality of chips; 
 decoding, at the DDR interface, the DDR burst using an error correction code (ECC) random error decoder; 
 wherein the ECC random error decoder fails to decode the DDR burst and in response:
 decoding the DDR burst using an ECC chip-kill decoder array comprising a plurality of ECC erasure decoders operating in parallel, wherein respective ECC erasure decoders of the plurality of ECC erasure decoders decodes the DDR burst assuming that a different chip of the plurality of chips of the DDR memory device has experienced a chip-kill event, in response to the decoding the DDR burst using an ECC chip-kill decoder array respective ones of the plurality of ECC erasure decoders generating a valid decoding solution to correct a number of random error symbols and to correct an erased portion of the memory block that corresponds to the chip assumed to have experienced a chip-kill event; 
 identifying a number of excess symbol corrections for the respective ones of the plurality of ECC erasure decoders generating a valid decoding solution wherein the identified number of excess symbol corrections is the number of random error symbol corrections made by the respective ECC ersure decoder during the decoding of the DDR burst; 
 
 identifying an ECC erasure decoder of the plurality of ECC erasure decoders having a fewest number of excess symbol corrections; and 
 selecting for output a decoded DDR burst from the identified ECC erasure decoder having the fewest number of excess symbol corrections. 
 
     
     
       2. The method of  claim 1 , wherein the fewest number of excess symbol corrections is in relation to a predetermined excess symbol correction threshold as a minimum required difference. 
     
     
       3. The method of  claim 1 , comprising enabling the ECC erasure decoder identified as having the fewest number of excess symbol corrections to decode subsequent DDR bursts received from the DDR memory device. 
     
     
       4. The method of  claim 1 , wherein if the ECC erasure decoder having the fewest number of excess symbol corrections cannot be identified by decoding a first DDR burst using the ECC chip-kill decoder array, the method comprising:
 receiving a plurality of subsequent DDR bursts comprising a plurality of encoded symbols; 
 decoding the plurality of subsequent DDR bursts at respective ones of the plurality of ECC erasure decoders and accumulating a number of excess symbol corrections made during the decoding of the plurality of subsequent DDR bursts at respective ones of the plurality of ECC erasure decoders; and 
 for respective ones of the plurality of ECC erasure decoders resulting in a valid decoding solution of the subsequent DDR bursts, identifying an ECC erasure decoder of the plurality of ECC erasure decoders having the fewest number of excess symbol corrections based upon the accumulated number of excess symbol corrections made during the decoding of the first DDR burst and the plurality of subsequent DDR burst. 
 
     
     
       5. The method of  claim 4 , wherein the fewest number of excess symbol corrections is in relation to a predetermined excess symbol correction threshold as a minimum required difference. 
     
     
       6. The method of  claim 1 , wherein the ECC random error decoder is a Reed-Solomon ECC random error decoder. 
     
     
       7. The method of  claim 1 , wherein respective ones of the plurality of ECC erasure decoders are Reed-Solomon ECC erasure decoders. 
     
     
       8. The method of  claim 1 , wherein a symbol correction capacity of the ECC random error decoder is greater than a symbol correction capacity of respective ones of the plurality of ECC erasure decoders. 
     
     
       9. The method of  claim 1 , wherein the DDR interface is a DDR4 interface or a DDR5 interface. 
     
     
       10. A double data rate (DDR) chip-kill decoder comprising:
 an error correction code (ECC) random error decoder to receive a DDR burst comprising a plurality of encoded symbols from a DDR memory device, the DDR memory device comprising a plurality of chips; 
 an ECC chip-kill decoder array comprising a plurality of ECC erasure decoders to decode the DDR burst when the ECC random error decoder fails to decode the DDR burst, wherein respective ECC erasure decoders of the plurality of ECC erasure decoders are to operate in parallel to decode the DDR burst assuming that a different chip of the plurality of chips of the DDR memory device has experienced a chip-kill event, in response to the decoding the DDR burst using the ECC chip-kill decoder array respective ones of the plurality of ECC erasure decoder to generate a valid decoding solution to correct a number of random error symbols and to correct an erased portion of the memory block that corresponds to the chip assumed to have experienced a chip-kill event; and 
 a decode selection logic circuit to:
 identify a number of excess symbol corrections for respective ones of the plurality of ECC erasure decoders generatinf a valid decoding solution, wherein the identified number of excess symbol corrections is number of random error symbol corrections made by the respective ECC erasure decoder diring the decoding of the DDR burst, 
 identify an ECC erasure decoder of the plurality of ECC erasure decoders having a fewest number of excess symbol corrections, and 
 select for output a decoded DDR burst from the ECC random error decoder when the decoding of the DDR burst using the ECC random error decoder does not fail to decode the DDR burst, or a decoded DDR burst from the identified ECC erasure decoder having the fewest number of excess symbol corrections when the decoding of the DDR burst using the ECC random error decoder fails to decode the DDR burst. 
 
 
     
     
       11. The DDR chip-kill decoder of  claim 10 , wherein the fewest number of excess symbol corrections is in relation to a predetermined excess symbol correction threshold as a minimum required difference. 
     
     
       12. The DDR chip-kill decoder of  claim 10 , wherein the ECC erasure decoder identified as having the fewest number of excess symbol corrections is to decode subsequent DDR bursts received from the DDR memory device. 
     
     
       13. The DDR chip-kill decoder of  claim 10 , wherein if the decode selection logic circuit is unable to identify the ECC erasure decoder having the fewest number of excess symbol corrections by decoding the encoded symbols of a first DDR burst, the decode selection logic circuit is to:
 receive a plurality of subsequent DDR bursts comprising a plurality of encoded symbols; 
 decode the plurality of subsequent DDR bursts at respective ones of the plurality of ECC erasure decoders and accumulate a number of excess symbol corrections made during the decoding of the plurality of subsequent DDR bursts; and 
 for respective ones of the plurality of ECC erasure decoders resulting in a valid decoding solution of the subsequent DDR bursts, identify an ECC erasure decoder of the plurality of ECC erasure decoders having the fewest number of excess symbol corrections based upon the accumulated number of excess symbol corrections made during the decoding of the first DDR burst and the plurality of subsequent DDR bursts by respective ones of the plurality of ECC erasure decoders. 
 
     
     
       14. The DDR chip-kill decoder of  claim 10 , wherein the ECC random error decoder is a Reed-Solomon ECC random error decoder. 
     
     
       15. The DDR chip-kill decoder of  claim 10 , wherein respective ones of the plurality of ECC erasure decoders are Reed-Solomon ECC erasure decoders. 
     
     
       16. The DDR chip-kill decoder of  claim 10 , wherein a symbol correction capacity of the ECC random error decoder is greater than a symbol correction capacity of respective ones of the plurality of ECC erasure decoders. 
     
     
       17. A memory controller comprising:
 a double data rate (DDR) interface in communication with one or more DDR memory devices, the DDR interface for receiving a DDR burst comprising a plurality of encoded symbols from the one or more DDR memory devices, wherein the one or more DDR memory devices comprises a plurality of chips; 
 a DDR chip-kill decoder in communication with the DDR interface, the DDR chip-kill decoder comprising:
 an error correction code (ECC) random error decoder to receive the DDR burst from the DDR interface; 
 an ECC chip-kill decoder array comprising a plurality of ECC erasure decoders to decode the DDR burst, wherein respective ones of the plurality of ECC erasure decoders are to operate in parallel to decode the DDR burst assuming that a different chip of the plurality of chips of the one or more DDR memory devices has experienced a chip-kill event in response to the decoding the DDR burst using the ECC chip-kill decoder array respective ones of the plurality of ECC erasure decoders to generate a valid decoding solution to correct a number of random error symbols and to correct an erased portion of the memory block that corresponds to the chip assumed to have experienced a chip-kill event; and 
 a decode selection logic circuit to:
 identify a number of excess symbol corrections for the respective ones of the plurality of ECC erasure decoders generating a valid decoding solution wherein the identified number of excess symbol corrections in the number of random error symbol corrections made by the respective ECC erasure decoder during the decoding of the DDR burst, 
 identify an ECC erasure decoder of the plurality of ECC erasure decoders having a fewest number of excess symbol corrections, and 
 select for output a decoded DDR burst from the ECC random error decoder when the decoding of the DDR burst using the ECC random error decoder does not fail to decode the DDR burst or a decoded DDR burst from the identified ECC erasure decoder having the fewest number of excess symbol corrections when the decoding of the DDR burst using the ECC random error decoder fails to decode the DDR burst. 
 
 
 
     
     
       18. The memory controller of  claim 17 , wherein the fewest number of excess symbol corrections is in relation to a predetermined excess symbol correction threshold as a minimum required difference. 
     
     
       19. The memory controller of  claim 17 , wherein the DDR interface is a DDR4 burst interface or a DDR5 burst interface. 
     
     
       20. The memory controller of  claim 17 , wherein the ECC random error decoder is a Reed-Solomon ECC random error decoder and respective ones of the plurality of ECC erasure decoders are Reed-Solomon ECC erasure decoders.