Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof

Abstract

A method is provided for preparing a semiconductor-on-insulator structure comprising a silicon nitride layer deposited by plasma deposition.

What is claimed is: 
     
       1. A method of preparing a multilayer structure, the method comprising:
 curing a handle dielectric layer comprising a flowable silazane, wherein the handle dielectric layer comprising the flowable silazane is in interfacial contact with a front surface of a single crystal silicon handle substrate, wherein the single crystal silicon handle substrate comprises two major, generally parallel surfaces, one of which is the front surface of the single crystal silicon handle substrate and the other of which is a back surface of the single crystal silicon handle substrate, a circumferential edge joining the front surface and the back surface of the single crystal silicon handle substrate, a central plane between the front surface and the back surface of the single crystal silicon handle substrate, and a bulk region between the front and back surfaces of the single crystal silicon handle substrate, wherein the handle dielectric layer is cured by irradiating the handle dielectric layer with light having a wavelength between about 185 nanometers and about 256 nanometers, and wherein the cured handle dielectric layer has a surface roughness, measured by a root mean square method over a 2 micrometer by 2 micrometer surface area, of less than 2 angstroms; 
 depositing a handle semiconductor nitride layer on the cured handle dielectric layer in interfacial contact with the front surface of the single crystal silicon handle substrate; and 
 bonding a donor dielectric layer in interfacial contact with a front surface of a single crystal semiconductor donor substrate to the handle semiconductor nitride layer to thereby form a bonded structure, wherein the single crystal semiconductor donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the semiconductor donor substrate and the other of which is a back surface of the semiconductor donor substrate, a circumferential edge joining the front and back surfaces of the semiconductor donor substrate, a central plane between the front and back surfaces of the semiconductor donor substrate, and a bulk region between the front and back surfaces of the semiconductor donor substrate, and further wherein the single crystal semiconductor donor substrate comprises a cleave plane. 
 
     
     
       2. The method of  claim 1  wherein the single crystal silicon handle substrate comprises a single crystal silicon wafer sliced from a single crystal silicon ingot grown by the Czochralski method or the float zone method. 
     
     
       3. The method of  claim 1  wherein the single crystal semiconductor donor substrate comprises single crystal silicon. 
     
     
       4. The method of  claim 1  wherein the single crystal semiconductor donor substrate comprises a single crystal silicon wafer sliced from a single crystal silicon ingot grown by the Czochralski method or the float zone method. 
     
     
       5. The method of  claim 1  wherein the handle semiconductor nitride layer is deposited by plasma enhanced chemical vapor deposition. 
     
     
       6. The method of  claim 1  wherein the handle semiconductor nitride layer comprises silicon nitride. 
     
     
       7. The method of  claim 6  wherein the silicon nitride has a molar ratio of silicon to nitride of between about 0.7 and about 1.8. 
     
     
       8. The method of  claim 1  wherein the handle semiconductor nitride layer has a thickness between about 500 angstroms and about 10,000 angstroms. 
     
     
       9. The method of  claim 1  wherein the handle dielectric layer has a thickness of at least about 10 nanometer thick, such as between about 10 nanometers and about 10,000 nanometers, between about 10 nanometers and about 5,000 nanometers, between 50 nanometers and about 400 nanometers, or between about 100 nanometers and about 400 nanometers, such as about 50 nanometers, 100 nanometers, or 200 nanometers. 
     
     
       10. The method of  claim 1  wherein the flowable silazane is a perhydropolysilazane. 
     
     
       11. The method of  claim 1  wherein the flowable silazane is a polysilazane derivatized with an R group comprising hydrocarbyl having from one to 12 carbon atoms or an R group comprising aromatic groups having from three to 12 carbon atoms. 
     
     
       12. The method of  claim 1  wherein the donor dielectric layer comprises a material selected from the group consisting of silicon dioxide, silicon oxynitride, silicon nitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and any combination thereof. 
     
     
       13. The method of  claim 1  the donor dielectric layer comprises a material selected from the group consisting of silicon dioxide, silicon oxynitride, silicon nitride, and any combination thereof. 
     
     
       14. The method of  claim 1  wherein the donor dielectric layer comprises a multilayer, each insulating layer within the multilayer comprising a material selected from the group consisting of silicon dioxide, silicon oxynitride, and silicon nitride. 
     
     
       15. The method of  claim 1  wherein the donor dielectric layer comprises an insulating layer having a thickness of at least about 10 nanometer thick, such as between about 10 nanometers and about 10,000 nanometers, between about 10 nanometers and about 5,000 nanometers, between 50 nanometers and about 400 nanometers, or between about 100 nanometers and about 400 nanometers, such as about 50 nanometers, 100 nanometers, or 200 nanometers. 
     
     
       16. The method of  claim 1  further comprising annealing the bonded structure at a temperature and for a duration sufficient to strengthen the bond between the donor dielectric layer of the single crystal semiconductor donor substrate and the handle nitride layer of the single crystal silicon handle substrate. 
     
     
       17. The method of  claim 16  wherein annealing occurs at a temperature between about 300° C. and about 700° C., such as from about 400° C. to about 600° C., such as between about 400° C. and about 450° C., or even between about 450° C. and about 600° C., or between about 350° C. and about 450° C. 
     
     
       18. The method of  claim 17  wherein annealing occurs at a pressure between about 0.5 MPa and about 200 MPa, Such as between about 0.5 MPa and about 100 MPa, such as between about 0.5 MPa and about 50 MPa, or between about 0.5 MPa and about 10 MPa, or between about 0.5 MPa and about 5 MPa. 
     
     
       19. The method of  claim 16  further comprising mechanically cleaving the bonded structure at the cleave plane of the single crystal semiconductor donor substrate to thereby prepare a cleaved structure comprising the single crystal silicon handle substrate, the handle dielectric layer, the handle semiconductor nitride layer, the donor dielectric layer, and a single crystal semiconductor device layer.