Memory component provided with a test interface

Abstract

A memory component comprises a memory unit including an array of memory cells, a controller of the memory unit, and a JTAG test interface including a plurality of contact pads adapted to connect the memory component with a host device and/or a test machine, wherein the test interface further comprises a plurality of test registers, which are configured to store the operating instructions for performing the test of the memory component, and wherein those test registers are organized in a matrix configuration, each row of the matrix being associated with a specific address. A related System-On-Chip device and a related method are further disclosed.

The invention claimed is: 
     
       1. An apparatus, comprising:
 a plurality of test registers configured to store operating instructions for performing a test of a memory component, wherein the operating instructions include current and voltage settings for performing the test; 
 a memory component having an array of memory cells; 
 a controller; and 
 a JTAG test interface having a number of contact pads to connect the array of memory cells of the memory component with a host device and/or a test machine, wherein the number of contact pads include an analog pad to provide voltage or current to the memory component. 
 
     
     
       2. The apparatus of  claim 1 , wherein the JTAG test interface includes the plurality of test registers. 
     
     
       3. The apparatus of  claim 1 , wherein the plurality of test registers are organized in a matrix configuration. 
     
     
       4. The apparatus of  claim 3 , wherein the matrix configuration includes a plurality of rows, wherein each respective row is associated with a different address of the memory component. 
     
     
       5. The apparatus of  claim 1 , wherein the plurality of test registers comprise latches. 
     
     
       6. The apparatus of  claim 1 , wherein the plurality of test registers comprise flip flop circuitry. 
     
     
       7. An apparatus, comprising:
 a plurality of test registers configured to store operating instructions for performing a test of a memory component, wherein the operating instructions include a signal path in the memory component for performing the test; 
 a memory component having an array of memory cells; 
 a controller; and 
 a JTAG test interface having a number of contact pads to connect the array of memory cells of the memory component with a host device and/or a test machine, wherein the number of contact pads include a pad to ask for test execution to trigger a start of a test of the memory component. 
 
     
     
       8. The apparatus of  claim 7 , wherein the apparatus is a system-on-chip device. 
     
     
       9. The apparatus of  claim 7 , wherein the memory component is a structurally independent semiconductor device. 
     
     
       10. The apparatus of  claim 7 , wherein the memory component includes a number of communication pads. 
     
     
       11. The apparatus of  claim 7 , wherein the controller is to perform reading and programming operations on the memory component using the JTAG test interface. 
     
     
       12. A method, comprising:
 loading operating instructions for performing a test of a memory component in a test register, wherein the memory component includes an array of memory cells, and the operating instructions include:
 current and voltage settings for performing the test; and 
 a signal path in the memory component for performing the test; and 
 
 performing the test of the memory component using a device busy pad that indicates that the memory component is busy. 
 
     
     
       13. The method of  claim 12 , wherein the method includes performing the test of the memory component using:
 an analog pad that provides voltage or current to the memory component; and 
 a pad that asks for execution of the test. 
 
     
     
       14. The method of  claim 12 , wherein the method includes connecting pads of the memory component with a host device. 
     
     
       15. The method of  claim 12 , wherein the method includes connecting pads of the memory component with a test machine. 
     
     
       16. The method of  claim 12 , wherein the method includes addressing the test register to retrieve information associated with the test. 
     
     
       17. The method of  claim 12 , wherein the method includes loading the operating instructions for performing the test in the test register upon initiating a test mode for the memory component. 
     
     
       18. The method of  claim 12 , wherein the method includes performing the test using JTAG protocol. 
     
     
       19. The method of  claim 12 , wherein the method includes preventing selection of the test register by a user while the test is being performed.