Three-dimensional memory devices and methods of manufacturing thereof

Abstract

A semiconductor device includes a first conductor structure extending along a lateral direction. The semiconductor device includes a first memory film that extends along a vertical direction and is in contact with the first conductor structure. The semiconductor device includes a first semiconductor film that extends along the vertical direction and is in contact with the first memory film. Ends of the first semiconductor film align with ends of the first memory film, respectively. The semiconductor device includes a second conductor structure extending along the vertical direction. The semiconductor device includes a third conductor structure extending along the vertical direction. The semiconductor device includes a fourth conductor structure extending along the vertical direction. The second and fourth conductor structures are coupled to the ends of the first semiconductor film, and the third conductor structure is coupled to a portion of the first semiconductor film between its ends.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a first conductor structure extending along a lateral direction; 
 a first memory film extending along a vertical direction, wherein the first memory film is in contact with the first conductor structure; 
 a first semiconductor film extending along the vertical direction, wherein the first semiconductor film is in contact with the first memory film, and ends of the first semiconductor film align with ends of the first memory film, respectively; 
 a second conductor structure extending along the vertical direction; 
 a third conductor structure extending along the vertical direction; and 
 a fourth conductor structure extending along the vertical direction; 
 wherein the second and fourth conductor structures are coupled to the ends of the first semiconductor film, respectively, and the third conductor structure is coupled to a portion of the first semiconductor film between the second and fourth conductor structures. 
 
     
     
       2. The semiconductor device of  claim 1 , further comprising:
 a fifth conductor structure extending along the lateral direction; 
 a second memory film extending along the vertical direction, wherein the second memory film is in contact with the fifth conductor structure; 
 a second semiconductor film extending along the vertical direction, wherein the second semiconductor film is in contact with the second memory film, and ends of the second semiconductor film align with ends of the second memory film, respectively; and 
 a sixth conductor structure extending along the vertical direction; 
 wherein the second and fourth conductor structures are coupled to the ends of the second semiconductor film, and the sixth conductor structure is coupled to a portion of the second semiconductor film between its ends. 
 
     
     
       3. The semiconductor device of  claim 2 , wherein the first and fifth conductor structures are electrically isolated from each other by at least a first portion and a second portion of a dielectric layer. 
     
     
       4. The semiconductor device of  claim 3 , wherein the first and second portions of the dielectric layer each extend along the vertical direction and the lateral direction. 
     
     
       5. The semiconductor device of  claim 2 , wherein the third and sixth conductor structures are electrically coupled to each other. 
     
     
       6. The semiconductor device of  claim 2 , wherein the second and fourth conductor structure are electrically isolated from each other. 
     
     
       7. The semiconductor device of  claim 2 , wherein
 the first conductor structure, a first portion of the first memory film, a first portion of the first semiconductor film, the second conductor structure, and the third conductor structure operate as a first memory cell; 
 the first conductor structure, a second portion of the first memory film, a second portion of the first semiconductor film, the fourth conductor structure, and the third conductor structure operate as a second memory cell; 
 the fifth conductor structure, a first portion of the second memory film, a first portion of the second semiconductor film, the second conductor structure, and the sixth conductor structure operate as a third memory cell; and 
 the fifth conductor structure, a second portion of the second memory film, a second portion of the second semiconductor film, the fourth conductor structure, and the sixth conductor structure operate as a fourth memory cell. 
 
     
     
       8. The semiconductor device of  claim 1 , wherein the first memory film and the first semiconductor film are each arranged as a portion of a circle. 
     
     
       9. The semiconductor device of  claim 1 , wherein the first memory film and the first semiconductor film are each arranged as a portion of an oval. 
     
     
       10. The semiconductor device of  claim 1 , wherein the first memory film and the first semiconductor film are each arranged as a portion of a rectangle. 
     
     
       11. The semiconductor device of  claim 1 , wherein the first memory film and the first semiconductor film are each arranged as a portion of a rhombus. 
     
     
       12. A memory device, comprising:
 a first memory cell; 
 a second memory cell; 
 a third memory cell; and 
 a fourth memory cell; 
 wherein the first memory cell includes a first portion of a first memory film and a first portion of a first semiconductor film, the first memory film and the first semiconductor film extending along a vertical direction; 
 wherein the second memory cell includes a second portion of the first memory film and a second portion of the first semiconductor film; 
 wherein the third memory cell includes a first portion of a second memory film and a first portion of a second semiconductor film, the second memory film and the second semiconductor film extending along the vertical direction; and 
 wherein the fourth memory cell includes a second portion of the second memory film and a second portion of the second semiconductor film. 
 
     
     
       13. The memory device of  claim 12 , wherein the first memory film and first semiconductor film are in contact with each other and collectively formed as a first portion of a curvature-based shape, and the second memory film and second semiconductor film are in contact with each other and collectively formed as a second portion of the curvature-based shape. 
     
     
       14. The memory device of  claim 12 , wherein the first memory film and first semiconductor film are in contact with each other and collectively formed as a first portion of a polygon-based shape, and the second memory film and second semiconductor film are in contact with each other and collectively formed as a second portion of the polygon-based shape. 
     
     
       15. The memory device of  claim 12 , further comprising:
 a first bit/source line extending along the vertical direction; 
 a second bit/source line extending along the vertical direction; 
 a third bit/source line extending along the vertical direction; and 
 a fourth bit/source line extending along the vertical direction; 
 wherein the first and second bit/source lines are electrically coupled to the first portion of the first semiconductor film, the second and third bit/source lines are electrically coupled to the second portion of the first semiconductor film, the third and fourth bit/source lines are electrically coupled to the second portion of the second semiconductor film, and the fourth and first bit/source lines are electrically coupled to the first portion of the second semiconductor film, and 
 wherein the second and fourth bit/source lines are electrically coupled to each other. 
 
     
     
       16. The memory device of  claim 12 , further comprising:
 a first word line extending along a lateral direction; and 
 a second word line extending along the lateral direction; 
 wherein the first word line is electrically coupled to the first semiconductor film through the first memory film, and the second word line is electrically coupled to the second semiconductor film through the second memory film. 
 
     
     
       17. A memory device, comprising:
 a first conductor structure extending along a lateral direction; 
 a first memory film extending along a vertical direction, wherein the first memory film is in contact with the first conductor structure; 
 a first semiconductor film extending along the vertical direction, wherein the first semiconductor film is in contact with the first memory film, and ends of the first semiconductor film align with ends of the first memory film, respectively; 
 a second conductor structure extending along the vertical direction; 
 a third conductor structure extending along the vertical direction; 
 a fourth conductor structure extending along the vertical direction, wherein the second and fourth conductor structures are coupled to the ends of the first semiconductor film, and the third conductor structure is coupled to a portion of the first semiconductor film between the second and fourth conductor structures; 
 a fifth conductor structure extending along the lateral direction; 
 a second memory film extending along the vertical direction, wherein the second memory film is in contact with the fifth conductor structure; 
 a second semiconductor film extending along the vertical direction, wherein the second semiconductor film is in contact with the second memory film, and ends of the second semiconductor film align with ends of the second memory film, respectively; and 
 a sixth conductor structure extending along the vertical direction, wherein the second and fourth conductor structures are coupled to the ends of the second semiconductor film, and the sixth conductor structure is coupled to a portion of the second semiconductor film between the second and fourth conductor structures. 
 
     
     
       18. The memory device of  claim 17 , wherein the first and fifth conductor structures are electrically isolated from each other by at least a first portion and a second portion of a dielectric layer. 
     
     
       19. The memory device of  claim 17 , wherein the third and sixth conductor structures are electrically coupled to each other. 
     
     
       20. The memory device of  claim 17 , wherein the second and fourth conductor structure are electrically isolated from each other.