Tunable CMOS circuit, template matching module, neural spike recording system, and fuzzy logic gate

Abstract

A tunable CMOS circuit comprising a CMOS element and a tunable load. The CMOS element is configured to receive an analogue input signal. The tunable load is connected to the CMOS element and configured to set a switch point of the CMOS element. The CMOS element is configured to output an output current that is largest when the analogue input signal is equal to the switch point. The combination of a CMOS element with a tunable load may also provide a hardware implementation of fuzzy logic. A fuzzy logic gate comprises an input node, a CMOS logic gate, a tunable load, and an output node. The input node is configured to receive an analogue input signal. The CMOS logic gate is connected to the input node. The tunable load is connected to the CMOS logic gate such that the tunable load is provided on a current path connected to the output node. The output node is configured to output an analogue output signal.

The invention claimed is: 
     
       1. A template matching module for determining a match between an analogue neural spike signal and a programmable template, the template matching module comprising:
 a sampling element configured to sample the analogue neural spike signal at a plurality of discrete moments in time to create a plurality of signal samples, and 
 a template row for storing a tunable template, the template row comprising:
 a plurality of template pixels, wherein each of the plurality of template pixels comprises a tunable complementary metal oxide semiconductor (CMOS) circuit configured to store a value, receive a respective one of the plurality of signal samples, determine whether the one of the plurality of signal samples matches the stored value, and output an output current; and 
 an output device configured to integrate the output currents outputted by the plurality of template pixels, wherein: 
 the tunable CMOS circuit comprises:
 a CMOS element configured to receive an analogue input signal, and 
 a tunable load connected to the CMOS element and configured to set a switch point of the CMOS element, 
 wherein the CMOS element is configured to output an output current, the output current being largest when the analogue input signal is equal to the switch point. 
 
 
 
     
     
       2. The template matching module of  claim 1 , wherein the tunable load comprises one or more memristors. 
     
     
       3. The template matching module of  claim 1 , wherein:
 the CMOS element comprises a first CMOS stage and a second CMOS stage, 
 the first CMOS stage is configured to receive the analogue input, 
 the output of the first CMOS stage is connected to the input of the second CMOS stage, and 
 the second CMOS stage is configured to draw a current that is largest when the analogue input signal is equal to the switch point. 
 
     
     
       4. The template matching module of  claim 3 , wherein:
 the first CMOS stage comprises a CMOS inverter, and/or 
 the second CMOS stage comprises a CMOS inverter. 
 
     
     
       5. The template matching module of  claim 3 , wherein:
 the CMOS element comprises an output stage configured to output the output current, and 
 the output stage is configured to output an output current that is proportional to the current drawn by the second CMOS stage, optionally wherein the output stage comprises a current mirror. 
 
     
     
       6. The template matching module of  claim 3 , wherein:
 the first CMOS stage is configured to output a midpoint signal, 
 the second CMOS stage is configured to draw a current that is largest when the midpoint signal is at a predetermined fixed value, and 
 the tunable load is connected to the first CMOS stage such that the first CMOS stage outputs a midpoint signal equal to the predetermined fixed value when the analogue input signal is equal to the switch point set by the tunable load. 
 
     
     
       7. The template matching module of  claim 3 , wherein:
 the first CMOS stage is configured to output a midpoint signal, and 
 the tunable load is connected to the second CMOS stage so as to set the value of the midpoint signal at which the current drawn by the second CMOS stage is largest. 
 
     
     
       8. The template matching module of  claim 7 , wherein the tunable load is connected in series to the second CMOS stage. 
     
     
       9. The template matching module of  claim 1 , wherein the CMOS element consists of six transistors and two memristors. 
     
     
       10. The template matching module of  claim 3 , further comprising an input range setter connected to the first CMOS stage, the input range setter being configured to match an input signal range of the first CMOS stage to an input signal range of the second CMOS stage. 
     
     
       11. The template matching module of  claim 1  comprising a plurality of template rows, wherein each template row is for storing a different programmable template, each template row comprising:
 a plurality of template pixels, wherein each of the plurality of template pixels comprises a tunable CMOS circuit configured to store a value, receive a respective one of the plurality of signal samples, determine whether the one of the plurality of signal samples matches the stored value, and output an output current; and 
 an output device configured to integrate the output currents outputted by the plurality of template pixels, wherein: 
 each of the tunable CMOS circuits comprises:
 a CMOS element configured to receive an analogue input signal, and 
 a tunable load connected to the CMOS element and configured to set a switch point of the CMOS element, 
 wherein the CMOS element is configured to output an output current, the output current being largest when the analogue input signal is equal to the switch point. 
 
 
     
     
       12. The template matching module of  claim 1 , further comprising a spike isolation module configured to receive analogue neuronal data and to isolate an analogue neural spike signal, or a succession of analogue neural spike signals, from the analogue neuronal data. 
     
     
       13. The template matching module of  claim 1 , wherein the output device of the template row or of each of the template rows comprises a capacitor that is configured to integrate the plurality of output currents that are outputted by the plurality of template pixels of the respective template row. 
     
     
       14. The template matching module of  claim 1 , wherein the output device of the template row or of each of the template rows is configured to indicate when the integral of the plurality of output currents that are outputted by the plurality of template pixels of the respective template row exceeds a threshold. 
     
     
       15. The template matching module of  claim 1  being implemented as an integrated circuit. 
     
     
       16. A method of using the template matching module of  claim 1 , the method comprising
 storing a template in the template row or one of the template rows by setting the switch point of each template pixel of the template row, 
 applying an analogue input signal at the input of the template matching module, and 
 indicating whether the analogue input signal matches the stored template. 
 
     
     
       17. A neural spike recording system for recording neuronal activity in-vivo, the neural spike recording system comprising:
 a neurological sensor configured to measure neuronal activity and output a corresponding analogue electrical signal, 
 signal processing circuitry configured to pre-process the analogue electrical signal so as to create pre-processed neuronal data, and 
 the template matching module of  claim 1 , the template matching module being configured to isolate a neural spike signal from the pre-processed neuronal data and determine whether the neural spike signal matches one of the stored templates.