Memory system using asymmetric source-synchronous clocking

Abstract

The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.

What is claimed is: 
     
       1. A circuit, comprising:
 delay circuitry having input circuitry to receive a first control signal, the delay circuitry responsive to the first control signal to delay a first input signal by a first delay value, the delay circuitry responsive to a change from the first control signal to a second control signal to delay a second input signal by a second delay value; 
 control circuitry to generate the first and second control signals; and 
 gating circuitry coupled to the control circuitry to conditionally gate the change from the first control signal to the second control signal based on an indicator of whether the first input signal has finished propagating through the delay circuitry. 
 
     
     
       2. The circuit of  claim 1 , wherein:
 the indicator comprises a signal derived from an output of the delay circuitry that corresponds to a delayed version of the first input signal. 
 
     
     
       3. The circuit of  claim 2 , wherein:
 the gating circuitry applies the change from the first control signal to the second control signal to the delay circuitry when the indicator signifies that the first input signal has finished propagating through the delay circuitry. 
 
     
     
       4. The circuit of  claim 3 , wherein:
 the first control signal and the second control signal comprise digitally coded values. 
 
     
     
       5. The circuit of  claim 3 , wherein the delay circuitry includes:
 a delay line including a chain of serially-connected delay elements; 
 selector circuitry responsive to a first control sub-code of the first control signal to select a delay interval bounded by an early delay value corresponding to an output from a first selected delay element of the delay line, and a late delay value corresponding to a second output from a second selected delay element of the delay line; and 
 an interpolator responsive to a second control sub-code of the first control signal to generate an interpolated delay within the delay interval. 
 
     
     
       6. The circuit of  claim 5 , wherein:
 the indicator comprises an enable signal derived from a last delay element of the delay line. 
 
     
     
       7. The circuit of  claim 5 , wherein:
 the second control signal comprises respective updated values to the first control sub-code and the second control sub-code; and 
 the gating circuitry comprises a set of holding latches to store the updated values to the first control sub-code and the second control sub-code until receipt of the enable signal. 
 
     
     
       8. An integrated circuit (IC), comprising:
 a timing generation circuit to generate a timing signal, the timing generation circuit including
 delay circuitry having input circuitry to receive a first control signal, the delay circuitry responsive to the first control signal to delay a first input signal by a first delay value, the delay circuitry responsive to a change from the first control signal to a second control signal to delay a second input signal by a second delay value; 
 control circuitry to generate the first and second control signals; 
 gating circuitry coupled to the control circuitry to conditionally gate the change from the first control signal to the second control signal based on an indicator of whether the first input signal has finished propagating through the delay circuitry; and 
 
 an interface to exchange data with another device at a data rate that is based on the timing signal. 
 
     
     
       9. The IC of  claim 8 , wherein:
 the indicator comprises a signal derived from an output of the delay circuitry that corresponds to a delayed version of the first input signal. 
 
     
     
       10. The IC of  claim 9 , wherein:
 the gating circuitry applies the change from the first control signal to the second control signal to the delay circuitry when the indicator signifies that the first input signal has finished propagating through the delay circuitry. 
 
     
     
       11. The IC of  claim 10 , wherein:
 the first control signal and the second control signal comprise digitally coded values. 
 
     
     
       12. The IC of  claim 10 , wherein the delay circuitry includes:
 a delay line including a chain of serially-connected delay elements; 
 selector circuitry responsive to a first control sub-code of the first control signal to select a delay interval bounded by an early delay value corresponding to an output from a first selected delay element of the delay line, and a late delay value corresponding to a second output from a second selected delay element of the delay line; and 
 an interpolator responsive to a second control sub-code of the first control signal to generate an interpolated delay within the delay interval. 
 
     
     
       13. The IC of  claim 12 , wherein:
 the indicator comprises an enable signal derived from a last delay element of the delay line. 
 
     
     
       14. The IC of  claim 12 , wherein:
 the second control signal comprises respective updated values to the first control sub-code and the second control sub-code; and 
 the gating circuitry comprises a set of holding latches to store the updated values to the first control sub-code and the second control sub-code until receipt of the enable signal. 
 
     
     
       15. A method of operation in an integrated circuit (IC), the method comprising:
 generating a timing signal, the generating including
 delaying, with a delay circuit, a first input signal by a first delay value specified by a first control signal; 
 conditionally gating a change from the first control signal to a second control signal based on an indicator of whether the first input signal has finished propagating through the delay circuit; and 
 exchanging data with another device at a data rate that is based on the timing signal. 
 
 
     
     
       16. The method of  claim 15 , further comprising:
 deriving the indicator from an output of the delay circuit, the indicator corresponding to a delayed version of the first input signal. 
 
     
     
       17. The method of  claim 16 , further comprising:
 applying the change from the first control signal to the second control signal when the indicator signifies that the first input signal has finished propagating through the delay circuit. 
 
     
     
       18. The method of  claim 17 , wherein:
 the first control signal and the second control signal comprise digitally coded values. 
 
     
     
       19. The method of  claim 17 , wherein the delaying includes:
 feeding the first input signal to a delay line including a chain of serially-connected delay elements; 
 selecting a delay interval bounded by an early delay value and a late delay value, the early delay value corresponding to an output from a first selected delay element of the delay line in response to a first control sub-code of the first control signal, the late delay value corresponding to a second output from a second selected delay element of the delay line; and 
 generating an interpolated delay within the delay interval in response to a second control sub-code of the first control signal. 
 
     
     
       20. The method of  claim 19 , wherein:
 deriving the indicator from a last delay element of the delay line, the indicator comprising an enable signal.