Concurrent compensation in a memory system

Abstract

An example method may be used to perform concurrent compensation in a memory array. The example method may include decoding a prime row address corresponding to a respective prime memory cell row of a first row section of a memory array mat to provide a prime section signal, and in response to a determination that the prime row address matches a defective prime row address, providing a redundant section signal corresponding to a respective redundant memory cell row of a second row section of the memory array mat. In response to the prime section signal, initiating a first threshold voltage compensation operation on first sensing circuitry coupled to the first row section; and in response to the redundant section signal indicating a defective prime row, initiating a second threshold voltage compensation operation on second sensing circuitry coupled to the second row section concurrent with the first threshold voltage compensation operation.

What is claimed is: 
     
       1. An apparatus comprising:
 a first memory region including a first memory cell mat including a first plurality of prime memory cells and a first plurality of redundant memory cells, a first sense amplifier coupled to each of the first plurality of prime memory cells and the first plurality of redundant memory cells; 
 a second memory region including a second memory cell mat including a second plurality of prime memory cells and a second plurality of redundant memory cells, a second sense amplifier coupled to each of the second plurality of prime memory cells and the second plurality of redundant memory cells; 
 a global row decoder coupled in common to the first and second memory regions, the global row decoder configured, in response to receipt of a first defective row address signal corresponds to a row of the first plurality of prime memory cells, to activate each of the first sense amplifier and the second sense amplifier; and 
 a row decoder configured, in response to receipt of the first defective row address signal, to provide a first prime section signal corresponding to the first plurality of prime memory cells to the global row decoder such that the first sense amplifier is activated, and to provide a second redundant section signal corresponding to the second plurality of redundant memory cells to the global row decoder such that the second sense amplifier is activated and a row of the second plurality of redundant memory cells is selected. 
 
     
     
       2. The apparatus of  claim 1 , wherein the first sense amplifier is configured to perform a threshold compensation when the first sense amplifier is activated, and the second sense amplifier performs a threshold compensation when the second sense amplifier is activated. 
     
     
       3. The apparatus of  claim 1 , wherein the row decoder is further configured, when receives the first defective row address signal, to activate a row of the second plurality of redundant memory cells and inhibit activation of a row of the first plurality of prime memory cells. 
     
     
       4. The apparatus of  claim 1 , wherein the row decoder comprises a predecoder configured to decode the first defective row address signal to set the first prime section signal. 
     
     
       5. The apparatus of  claim 1 , wherein the global row decoder comprises a first section control circuit configured to control activation of the first sense amplifier in response to the first prime section signal and a second section control circuit configured to control activation of the second sense amplifier in response to the second redundant section signal. 
     
     
       6. The apparatus of  claim 1 , wherein the row decoder is configured to provide one of the first prime section signal or the second redundant section signal as a final section signal; wherein the first section control circuit is configured to stop activation of the first sense amplifier in response to the final section signal being the second redundant section signal. 
     
     
       7. The apparatus of  claim 1 , wherein row decoder is configured to provide the first prime section signal and the second redundant section signal to the global decoder prior to the section signal. 
     
     
       8. The apparatus of  claim 1 , wherein the row decoder includes fuse data latches configured store defective row addresses, wherein the row decoder is configured to compare the first defective row address to the stored defective row addresses to select the second redundant section signal. 
     
     
       9. The apparatus of  claim 1 , wherein the row decoder includes a row latch configured to latch the first defective row address signal. 
     
     
       10. The apparatus of  claim 1 , wherein the global row decoder is further configured, in response to receipt of a first non-defective row address signal corresponds to another row of the first plurality of prime memory cells, to activate the first sense amplifier without activating the second sense amplifier. 
     
     
       11. An apparatus comprising:
 a memory cell array comprising a mat having a plurality of row sections, wherein each of the plurality of row sections includes respective prime memory cell rows and a respective redundant memory cell row; and 
 a global decoder comprising a plurality of control circuits each corresponding to a respective one of the plurality of row sections and each configured to receive a respective prime section signal and a respective redundant section signal from a row decoder, wherein, in response to the respective prime section signal, a first corresponding control circuit of the plurality of control circuits is configured to initiate a first threshold voltage compensation operation on first sensing circuitry coupled to a first respective one of the plurality of row sections, wherein, in response to the respective redundant section signal indicating a defective prime row, a second corresponding control circuit of the plurality of control circuits is configured to initiate a second threshold voltage compensation operation on second sensing circuitry coupled to a second respective one of the plurality of row sections concurrent with the first threshold voltage compensation operation. 
 
     
     
       12. The apparatus of  claim 11 , wherein the plurality of control circuits are each further configured to receive a respective section signal set based on detection of the defective prime row; wherein, in response to the respective section signal indicating the defective prime row, the first corresponding control circuit of the plurality of control circuits is configured to stop the first threshold voltage compensation operation. 
     
     
       13. The apparatus of  claim 12 , wherein in response to the respective section signal indicating a lack of defective prime row, the first corresponding control circuit of the plurality of control circuits is configured to continue the first threshold voltage compensation operation. 
     
     
       14. The apparatus of  claim 12 , wherein the plurality of control circuits are configured to receive the respective section signal after receipt of the respective prime section signal and the respective redundant section signal. 
     
     
       15. The apparatus of  claim 12 , further comprising a row decoder configured to receive a prime row address and to decode the prime row address to provide the respective prime section signal, wherein the prime row address corresponds to a respective prime row of memory cells of the first respective one of the plurality of row sections. 
     
     
       16. The apparatus of  claim 15 , wherein, in response to a determination that the prime row address matches the defective prime row address, the row decoder is further configured to provide the respective redundant section signal corresponding to the second corresponding control circuit of the plurality of control circuits. 
     
     
       17. A method comprising:
 decoding, at a row decoder of a memory, a prime row address to provide a prime section signal, wherein the prime row address corresponds to a respective prime memory cell row of a first row section of the plurality of row sections of a memory array mat; 
 in response to a determination that the prime row address matches a defective prime row address, providing a redundant section signal corresponding to a respective redundant memory cell row of a second row section of the plurality of row sections of the memory array mat; 
 in response to the prime section signal, initiating, via a first section control circuit of a global decoder, a first threshold voltage compensation operation on first sensing circuitry coupled to the first row section; and 
 in response to the redundant section signal indicating a defective prime row, initiating, via a second section control circuit of the global decoder, a second threshold voltage compensation operation on second sensing circuitry coupled to the second row section concurrent with the first threshold voltage compensation operation. 
 
     
     
       18. The method of  claim 17 , further comprising:
 after initiation of the first and second threshold voltage compensation operations, providing one of the prime section signal or the redundant section signal as a section signal to the first and second section control circuits based on whether or not the prime row address matches the defective prime row address; and 
 in response to the section signal being the redundant section signal, stopping the threshold voltage compensation operation. 
 
     
     
       19. The method of  claim 18 , further comprising, in response to the section signal being the prime section signal, continuing the first threshold voltage compensation operation. 
     
     
       20. The method of  claim 17 , further comprising clearing the redundant section signal in response a determination that the prime row address is different than the defective prime row address. 
     
     
       21. The method of  claim 17 , further comprising receiving, at the row decoder, the defective row address from fuse array data during an initialization operation.