Semiconductor device having reduced bump height variation

Abstract

A semiconductor device includes a first substrate and a second substrate. The semiconductor device includes a plurality of conductive pillars between the first and second substrates. The plurality of conductive pillars includes a first conductive pillar having a first width, wherein the first width is substantially uniform along an entire first height of the first conductive pillar, a second conductive pillar having a second width, wherein the second width is substantially uniform along an entire second height of the second conductive pillar, the first width is different from the second width, and the entire first height is equal to the entire second height, and a third conductive pillar having a third width, wherein the third width is substantially uniform along an entire third height of the third conductive pillar, and the third conductive pillar is between the first conductive pillar and the second conductive pillar in the first direction.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a first substrate; 
 a second substrate; and 
 a plurality of conductive pillars extending between the first substrate and the second substrate, wherein the plurality of conductive pillars comprises:
 a first conductive pillar having a first width measured in a first direction parallel to a surface of the first substrate, wherein the first width is substantially uniform along an entire first height of the first conductive pillar, 
 a second conductive pillar having a second width measure in the first direction, wherein the second width is substantially uniform along an entire second height of the second conductive pillar, the first width is different from the second width, and the entire first height is equal to the entire second height, and 
 a third conductive pillar having a third width measured in the first direction, wherein the third width is different from the first width, the third width is substantially uniform along an entire third height of the third conductive pillar, and the third conductive pillar is between the first conductive pillar and the second conductive pillar in the first direction. 
 
 
     
     
       2. The semiconductor device of  claim 1 , wherein a top-most surface of the first conductive pillar is coplanar with a top-most surface of the second conductive pillar. 
     
     
       3. The semiconductor device of  claim 1 , wherein a top-most surface of the first conductive pillar is coplanar with a top-most surface of the third conductive pillar. 
     
     
       4. The semiconductor device of  claim 1 , further comprising a conductive trace on the second substrate. 
     
     
       5. The semiconductor device of  claim 4 , further comprising a solder layer between the conductive trace and the first conductive pillar. 
     
     
       6. The semiconductor device of  claim 5 , wherein the solder layer directly contacts both the first conductive pillar and the conductive trace. 
     
     
       7. The semiconductor device of  claim 5 , further comprising a fourth conductive pillar, wherein the fourth conductive pillar is between the solder layer and the conductive trace. 
     
     
       8. The semiconductor device of  claim 1 , wherein each of the first conductive pillar, the second conductive pillar and the third conductive pillar comprises copper. 
     
     
       9. A semiconductor device comprising:
 a first substrate; 
 a plurality of conductive pillars extending from the first substrate, wherein the plurality of conductive pillars comprises:
 a first conductive pillar having a first width measured in a first direction parallel to a surface of the first substrate, wherein the first width is substantially uniform along an entire first height of the first conductive pillar, 
 a second conductive pillar having a second width measure in the first direction, wherein the second width is substantially uniform along an entire second height of the second conductive pillar, the first width is different from the second width, and the entire first height is equal to the entire second height, and 
 a third conductive pillar having a third width measured in the first direction, wherein the third width is different from the first width, the third width is substantially uniform along an entire third height of the third conductive pillar, and the third conductive pillar is between the first conductive pillar and the second conductive pillar in the first direction; and 
 
 a plurality of under bump metallurgy (UBM) layers, wherein each UBM layer of the plurality of UBM layer is between the first substrate and a corresponding conductive pillar of the plurality of conductive pillars. 
 
     
     
       10. The semiconductor device of  claim 9 , wherein a first UBM layer of the plurality of UBM layers has the first width, a second UBM layer of the plurality of UBM layers has the second width, and a third UBM layer of the plurality of UBM layers has the third width. 
     
     
       11. The semiconductor device of  claim 9 , further comprising:
 a second substrate; and 
 a conductive trace along the second substrate. 
 
     
     
       12. The semiconductor device of  claim 11 , further comprising a solder layer directly contacting the third conductive pillar and the conductive trace. 
     
     
       13. The semiconductor device of  claim 11 , further comprising:
 a solder layer between the second conductive pillar and the conductive trace; and 
 a fourth conductive pillar between the solder layer and the conductive trace. 
 
     
     
       14. The semiconductor device of  claim 9 , wherein the third conductive pillar is closer to an edge of the first substrate than the first conductive pillar. 
     
     
       15. The semiconductor device of  claim 9 , wherein the first width is about 5% to about 50% greater than the second width. 
     
     
       16. The semiconductor device of  claim 9 , wherein the third width is greater than the second width. 
     
     
       17. A semiconductor device comprising:
 a first substrate; 
 a second substrate; 
 a first plurality of conductive pillars extending between the first substrate and the second substrate, wherein the first plurality of conductive pillars comprises:
 a first conductive pillar having a first width measured in a first direction parallel to a surface of the first substrate, wherein the first width is substantially uniform along an entire first height of the first conductive pillar, 
 a second conductive pillar having a second width measure in the first direction, wherein the second width is substantially uniform along an entire second height of the second conductive pillar, the first width is different from the second width, and the entire first height is equal to the entire second height, and 
 a third conductive pillar having a third width measured in the first direction, wherein the third width is substantially uniform along an entire third height of the third conductive pillar, and the third conductive pillar is between the first conductive pillar and the second conductive pillar in the first direction; 
 
 a plurality of conductive traces on the second substrate, wherein the plurality of conductive traces comprises:
 a first conductive trace electrically connected to the first conductive pillar; 
 a second conductive trace electrically connected to the second conductive pillar; and 
 a third conductive trace electrically connected to the third conductive pillar; and 
 
 a plurality of solder layers, wherein the plurality of solder layers comprises:
 a first solder layer between the first conductive pillar and the first conductive trace; 
 a second solder layer between the second conductive pillar and the second conductive trace; and 
 a third solder layer between the third conductive pillar and the third conductive trace. 
 
 
     
     
       18. The semiconductor device of  claim 17 , wherein the first solder layer is separated from the second solder layer. 
     
     
       19. The semiconductor device of  claim 17 , wherein the first solder layer directly contacts the first conductive pillar and the first conductive trace, the second solder layer directly contacts the second conductive pillar and the second conductive trace, and the third solder layer directly contacts the third conductive pillar and the third conductive trace. 
     
     
       20. The semiconductor device of  claim 17 , further comprising a second plurality of conductive pillars, wherein the second plurality of conductive pillars comprises:
 a fourth conductive pillar between the first solder layer and the first conductive trace; 
 a fifth conductive pillar between the second solder layer and the second conductive trace; and 
 a sixth conductive pillar between the third solder layer and the third conductive trace.