US11922537B2ActiveUtilityA1

Resiliency schemes for distributed storage systems

Assignee: WEKA IO LTDPriority: Jun 19, 2018Filed: Dec 30, 2022Granted: Mar 5, 2024
Est. expiryJun 19, 2038(~11.9 yrs left)· nominal 20-yr term from priority
G06T 1/60G06F 11/004G06F 11/1076G06F 13/4221G06F 16/13G06F 16/182G06T 1/20G06F 2211/1028G06F 2213/0026G06F 11/108G06F 16/1847G06F 16/188
83
PatentIndex Score
0
Cited by
32
References
20
Claims

Abstract

A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices is operably coupled to one or more of a plurality of storage devices. A plurality of failure resilient stripes is distributed across the plurality of storage devices such that each of the plurality of failure resilient stripes spans a plurality of the storage devices. A graphics processing unit is operable to access data files from the failure resilient stripes, while bypassing a kernel page cache. Furthermore, these data files may be accessed in parallel by the graphics processing unit.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A system comprising:
 a storage system comprising a plurality of non-volatile memory devices, wherein:
 a plurality of device groups are designated according to the plurality of non-volatile memory devices; 
 data is stored in the storage system via a plurality of failure-protected stripes; 
 each of the plurality of failure-protected stripes comprises a plurality of storage blocks; 
 each non-volatile memory device, in a particular device group, comprises only one storage block of a particular failure-protected stripe; and 
 no two failure-protected stripes, of the plurality of failure-protected stripes, comprise a plurality of storage blocks located in the same device group; and 
 
 a server comprising a graphics processing device, wherein the server is operable to access a plurality of storage blocks in parallel while bypassing a kernel page cache. 
 
     
     
       2. The system of  claim 1 , wherein the server comprises a volatile memory device. 
     
     
       3. The system of  claim 1 , wherein the server is operable to access the plurality of storage blocks via an interface node comprising a PCIe interface. 
     
     
       4. The system of  claim 1 , wherein the server is operable to access the plurality of storage blocks via an interface node comprising a network interface. 
     
     
       5. The system of  claim 1 , wherein the server comprises a backend that is operable to manage data in a volatile memory device. 
     
     
       6. The system of  claim 1 , wherein the server comprises a frontend that is operable to determine a location of data required for a graphics operation. 
     
     
       7. The system of  claim 1 , wherein the graphics processing device is operable to receive data via an interface node. 
     
     
       8. The system of  claim 1 , wherein the server comprises a frontend that is operable to indicate to a graphics processing unit (GPU) that data required for a graphics operation is available. 
     
     
       9. The system of  claim 1 , wherein the storage system is operable to determine that data required for a graphics operation is located in a failure-protected stripe. 
     
     
       10. The system of  claim 1 , wherein the storage system comprises a frontend that is operable to indicate to a graphics processing unit (GPU) that data required for a graphics operation is available in the server. 
     
     
       11. A method comprising:
 building a plurality of failure-protected stripes, in a storage system, wherein:
 a plurality of device groups are designated according to a plurality of non-volatile memory devices, 
 each of the plurality of failure-protected stripes comprises a plurality of storage blocks, 
 each storage block of the plurality of storage blocks is located in a different non-volatile memory device in of a device group, 
 no two failure-protected stripes of the plurality of failure-protected stripes comprises a plurality of storage blocks located in the same device group; 
 
 communicating data of the plurality of storage blocks, of a particular failure-protected stripe, in parallel, between the storage system and a server while bypassing a kernel page cache; and 
 performing a graphics operation on the data using a graphics processing device in the server. 
 
     
     
       12. The method of  claim 11 , wherein the server comprises a volatile memory device. 
     
     
       13. The method of  claim 11 , wherein the server is operable to access the storage system via an interface node comprising a PCIe interface. 
     
     
       14. The method of  claim 11 , wherein the server is operable to access the storage system via an interface node comprising a network interface. 
     
     
       15. The method of  claim 11 , wherein the server comprises a backend that is operable to manage data in a volatile memory device. 
     
     
       16. The method of  claim 11 , wherein the method comprises determining a location of data required for the graphics operation. 
     
     
       17. The method of  claim 11 , wherein the method comprises receiving data, at the graphics processing device, via a network interface. 
     
     
       18. The method of  claim 11 , wherein the method comprises indicating to a graphics processing unit (GPU) that data required for the graphics operation is available. 
     
     
       19. The method of  claim 11 , wherein the method comprises determining, by the memory system, that data required for the graphics operation is located in a failure-protected stripe. 
     
     
       20. The method of  claim 11 , wherein the method comprises indicating, by a frontend of the memory system, that data required for the graphics operation is available in the server.

Join the waitlist — get patent alerts

Track US11922537B2 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.