US11899982B2ActiveUtilityA1

Command block management

Assignee: MICRON TECHNOLOGY INCPriority: Oct 16, 2018Filed: Jan 24, 2023Granted: Feb 13, 2024
Est. expiryOct 16, 2038(~12.2 yrs left)· nominal 20-yr term from priority
G06F 3/0659G06F 3/0604G06F 3/0673G06F 21/79G06F 12/1441G06F 12/1466G06F 11/073G06F 2212/7204G06F 2212/1016G06F 2212/1028G06F 12/0223G06F 11/0751G06F 11/0793G06F 11/0772G06F 2201/81G06F 11/0727G06F 12/0284G06F 2212/1032Y02D10/00G06F 3/0614G06F 3/0622G06F 3/0634G06F 3/0683
74
PatentIndex Score
0
Cited by
34
References
20
Claims

Abstract

Methods, systems, and devices for command block management are described. A memory device may receive a command (e.g., from a host device). The memory device may determine whether the command is defined by determining if the command is included within a set of defined commands. In the case that a received command is absent from the set of defined commands (e.g., the command is undefined), the memory device may block the command from being decoded for execution by the memory device. In some cases, the memory device may switch from a first operation mode to a second operation mode based on receiving an undefined command. The second operation mode may restrict an operation of the memory device, while the first mode may be less restrictive, in some cases. Additionally or alternatively, the memory device may indicate the undefined command to another device (e.g., the host device).

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method, comprising:
 receiving, at a memory device comprising a memory die, a command; 
 determining that the command is absent from a set of valid commands based at least in part on evaluating the command and the set of valid commands; 
 setting a mode register to a value indicating a safe mode of operation for the memory device, the safe mode allowing execution of a read command and restricting execution of a write command; and 
 blocking, based at least in part on determining that the command is absent from the set of valid commands, the command from being decoded. 
 
     
     
       2. The method of  claim 1 , further comprising:
 switching from a first mode of operation of the memory device to the safe mode of operation of the memory device based at least in part on setting the mode register to the value. 
 
     
     
       3. The method of  claim 2 , further comprising:
 restricting access to one or more addresses of the memory die. 
 
     
     
       4. The method of  claim 2 , further comprising:
 operating one or more banks of the memory die in a self-refresh mode based at least in part on switching to the safe mode of operation. 
 
     
     
       5. The method of  claim 2 , further comprising:
 restricting execution for one or more commands of the set of valid commands based at least in part on switching to the safe mode of operation. 
 
     
     
       6. The method of  claim 2 , further comprising:
 receiving, while operating in the safe mode, a command sequence for resetting the memory device to the first mode; and 
 switching the memory device from the safe mode to the first mode based at least in part on receiving the command sequence. 
 
     
     
       7. The method of  claim 1 , further comprising:
 transmitting an indication that the command is absent from the set of valid commands. 
 
     
     
       8. A method, comprising:
 receiving, at a memory device comprising a memory die, a plurality of commands; 
 determining whether each command of the plurality of commands is included in a set of defined commands for a memory array of the memory die; 
 decoding a first command of the plurality of commands for execution on the memory array of the memory die based at least in part on determining that the first command is included in the set of defined commands; 
 setting a mode register to a value based at least in part on determining that a second command of the plurality of commands is absent from the set of defined commands, the value indicating a safe mode of operation for the memory device, the safe mode allowing execution of a read command and restricting execution of a write command; and 
 blocking the second command of the plurality of commands from being decoded based at least in part on determining that the second command is absent from the set of defined commands. 
 
     
     
       9. The method of  claim 8 , further comprising:
 determining a quantity of commands of the plurality of commands that are absent from the set of defined commands; and 
 comparing the quantity to a threshold. 
 
     
     
       10. The method of  claim 9 , further comprising:
 switching from a first mode of operation of the memory device to the safe mode of operation of the memory device based at least in part on determining that the quantity satisfies the threshold. 
 
     
     
       11. The method of  claim 9 , further comprising:
 transmitting an indication that the quantity satisfies the threshold. 
 
     
     
       12. The method of  claim 9 , further comprising:
 receiving a signal indicating the threshold. 
 
     
     
       13. The method of  claim 8 , further comprising:
 storing one or more commands of the plurality of commands based at least in part on determining that the one or more commands are absent from the set of defined commands. 
 
     
     
       14. The method of  claim 8 , further comprising:
 storing the set of defined commands at the memory device. 
 
     
     
       15. An apparatus, comprising:
 a memory array; 
 circuitry operable to receive a command; and 
 a decoder coupled with the circuitry and the memory array and operable to decode the command received from the circuitry for execution by the apparatus, 
 wherein the apparatus is operable to:
 determine that the command is absent from a set of valid commands based at least in part on evaluating the command and the set of valid commands; 
 set a mode register to a value indicating a safe mode of operation for the apparatus, the safe mode allowing execution of a read command and restricting execution of a write command; and 
 block, based at least in part on determining that the command is absent from the set of valid commands, the command from being decoded. 
 
 
     
     
       16. The apparatus of  claim 15 , wherein the apparatus is operable to:
 switch from a first mode of operation of the apparatus to the safe mode of operation of the apparatus based at least in part on setting the mode register to the value. 
 
     
     
       17. The apparatus of  claim 16 , wherein the apparatus is operable to:
 restrict access to one or more addresses of the memory array. 
 
     
     
       18. The apparatus of  claim 16 , wherein the apparatus is operable to:
 operate one or more banks of the memory array in a self-refresh mode based at least in part on switching to the safe mode of operation. 
 
     
     
       19. The apparatus of  claim 16 , wherein the apparatus is operable to:
 restrict execution for one or more commands of the set of valid commands based at least in part on switching to the safe mode of operation. 
 
     
     
       20. The apparatus of  claim 16 , wherein the apparatus is operable to:
 receive, while operating in the safe mode, a command sequence for resetting the apparatus to the first mode; and 
 switch the apparatus from the safe mode to the first mode based at least in part on receiving the command sequence.

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