Semiconductor memory device

Abstract

A semiconductor memory device according to an embodiment includes memory cell transistors, a word line, and a controller. A memory cell transistor whose threshold voltage is included in first and second states store first and second data, respectively. In a verify operation of the first data, during application of a verify high voltage of the first data to the word line, the controller is configured to determine whether or not a threshold voltage of a memory cell transistor to which the first data is to be written exceeds the verify high voltage of the first data, and also determine whether or not a threshold voltage of a memory cell transistor to which the second data is to be written exceeds a verify low voltage of the second data.

The invention claimed is: 
     
       1. A semiconductor memory device comprising:
 a plurality of memory cell transistors each capable of storing a plurality of bits of data, a threshold voltage of each of the memory cell transistors being included in one of a plurality of states, the states including a first state and a second state, the second state being higher than the first state, a memory cell transistor whose threshold voltage is included in the first state storing first data, and a memory cell transistor whose threshold voltage is included in the second state storing second data; 
 a word line coupled to the memory cell transistors; and 
 a controller configured to perform a write operation that includes a plurality of program loops each including a program operation and a verify operation, 
 wherein 
 a verify low voltage and a verify high voltage higher than the verify low voltage are set for each of the states, and 
 in a verify operation of the first data, during application of a verify high voltage of the first data to the word line, the controller determines whether or not a threshold voltage of a memory cell transistor to which the first data is to be written exceeds the verify high voltage of the first data, and also determine whether or not a threshold voltage of a memory cell transistor to which the second data is to be written exceeds a verify low voltage of the second data. 
 
     
     
       2. The device of  claim 1 , further comprising:
 a plurality of bit lines coupled to the memory cell transistors, respectively, 
 wherein 
 in the verify operation, for each state of a write target, the controller is configured to: 
 set a memory cell transistor determined to have a threshold voltage equal to or lower than the verify low voltage, as a first program target; 
 set a memory cell transistor determined to have a threshold voltage exceeding the verify low voltage and being equal to or lower than the verify high voltage, as a second program target; and 
 set a memory cell transistor determined to have a threshold voltage exceeding the verify high voltage as program-inhibit, and 
 while a program voltage is being applied to the word line in the program operation, the controller is configured to: 
 apply a first voltage to a bit line coupled to the memory cell transistor of the first program target, 
 apply a second voltage higher than the first voltage to a bit line coupled to the memory cell transistor set as the second program target; and 
 apply a third voltage higher than the second voltage to a memory cell transistor set as program-inhibit. 
 
     
     
       3. The device of  claim 1 , wherein
 the first state and the second state are adjacent to each other. 
 
     
     
       4. The device of  claim 1 , wherein
 another state is set between the first state and the second state. 
 
     
     
       5. The device of  claim 1 , wherein
 the states include a third state and a fourth state, the fourth state is higher than the third state, a memory cell transistor whose threshold voltage is included in the third state stores third data, and a memory cell transistor whose threshold voltage is included in the fourth state stores fourth data, 
 in a verify operation of the third data, during application of a verify high voltage of the third data to the word line, the controller is configured to determine whether or not a threshold voltage of a memory cell transistor to which the third data is to be written exceeds the verify high voltage, and also determine whether or not a threshold voltage of a memory cell transistor to which the fourth data is to be written exceeds the verify low voltage, and 
 states set between the first state and the second state are different in number from states set between the third state and the fourth state. 
 
     
     
       6. The device of  claim 5 , wherein
 the first state and the second state are adjacent to each other, and 
 at least one state is set between the third state and the fourth state. 
 
     
     
       7. The device of  claim 1 , wherein
 in the verify operation of the first data, the controller is configured to execute a first determination and a second determination in parallel, 
 in the first determination, the controller is configured to determine whether or not the threshold voltage of the memory cell transistor to which the first data is to be written exceeds the verify high voltage of the first data, and 
 in the second determination, the controller is configured to determine whether or not the threshold voltage of the memory cell transistor to which the second data is to be written exceeds the verify low voltage of the second data. 
 
     
     
       8. The device of  claim 7 , wherein
 in the verify operation of the first data, the controller is configured to execute the first determination and the second determination simultaneously. 
 
     
     
       9. The device of  claim 7 , wherein
 the verify high voltage of the first data and the verify low voltage of the second data are equal to each other. 
 
     
     
       10. The device of  claim 1 , further comprising:
 a plurality of bit lines coupled to the memory cell transistors, respectively; 
 a first sense circuit coupled to a first bit line included among the bit lines, the first sense circuit including a first sense node, and the first sense circuit configured to determine a threshold voltage of a first memory cell transistor coupled to the first bit line, based on a voltage of the first sense node; and 
 a second sense circuit coupled to a second bit line included among the bit lines, the second sense circuit including a second sense node, the second sense circuit configured to determine a threshold voltage of a second memory cell transistor coupled to the second bit line, based on a voltage of the second sense node, 
 wherein 
 in the write operation, where the controller is configured to write the first data and the second data to the first memory cell transistor and the second memory cell transistor, respectively, a discharge time of the first sense node used for determining whether a threshold voltage of the first memory cell transistor exceeds the verify high voltage of the first data and a discharge time of the second node used for determining whether not a threshold voltage of the second memory cell transistor exceeds the verify low voltage of the second data are different from each other. 
 
     
     
       11. The device of  claim 10 , wherein
 in the verify operation of the first data, the controller 
 first charges the first sense node and then discharges the first sense node for a first time, before a determination is made as to whether or not the threshold voltage of the first memory cell transistor exceeds the verify high voltage of the first data, and 
 first charges the second sense node and then discharges the second sense node for a second time longer than the first time, before a determination is made as to whether or not the threshold voltage of the second memory cell transistor exceeds the verify low voltage of the second data. 
 
     
     
       12. The device of  claim 10 , wherein
 in the verify operation of the first data, the controller 
 first charges the first sense node and the second sense node and then discharges the first sense node and the second sense node for a first time, before a determination is made as to whether or not the threshold voltage of the first memory cell transistor exceeds the verify high voltage of the first data, and 
 discharges the second sense node for a third time without charging the second sense node, after a determination is made as to whether or not the threshold voltage of the first memory cell transistor exceeds the verify high voltage of the first data and before a determination is made as to whether or not the threshold voltage of the second memory cell transistor exceeds the verify low voltage of the second data. 
 
     
     
       13. The device of  claim 10 , wherein
 in the verify operation of the first data, the controller 
 first charges the first sense node and then discharges the first sense node for a first time, before a determination is made as to whether or not the threshold voltage of the first memory cell transistor exceeds the verify high voltage of the first data, and 
 first charges the second node and then discharges the second node for a fourth time shorter than the first time, before a determination is made as to whether or not the threshold voltage of the second memory cell transistor exceeds the verify low voltage of the second data. 
 
     
     
       14. The device of  claim 10 , wherein
 in the verify operation of the first data, the controller 
 first charges the first sense node and the second sense node and then discharges the first sense node and the second sense node for a fourth time, before a determination is made as to whether or not the threshold voltage of the second memory cell transistor exceeds the verify low voltage of the second data, and 
 discharges the first sense node and the second sense node for a fifth time without charging the first and second sense node, after a determination is made as to whether or not the threshold voltage of the second memory cell transistor exceeds the verify low voltage of the second data and before a determination is made as to whether or not the threshold voltage of the first memory cell transistor exceeds the verify high voltage of the first data. 
 
     
     
       15. The device of  claim 2 , wherein
 the states include a fifth state, a memory cell transistor whose threshold voltage is included in the fifth state stores fifth data, 
 where at least a first condition, a second condition and a third condition are satisfied in the repetition of the program loop, the controller is configured to set a memory cell transistor to which the fifth data is to be written as the second program target, 
 the first condition is that a threshold voltage of the memory cell transistor to which the fifth data is to be written does not exceed a verify high voltage, 
 the second condition is that a verify low voltage of the fifth data is not determined as being exceeded in an immediately preceding program loop, and 
 the third condition is that a current number of program loops is equal to or greater than a first number. 
 
     
     
       16. The device of  claim 2 , wherein
 the states include a sixth state and a seventh state, a memory cell transistor whose threshold voltage is included in the sixth state stores sixth data, and a memory cell transistor whose threshold voltage is included in the seventh state stores seventh data, 
 where at least a fourth condition, a fifth condition and a sixth condition are satisfied in the repetition of the program loop, the controller is configured to set a memory cell transistor to which the fifth data is to be written as the second program target, 
 the fourth condition is that a threshold voltage of the memory cell transistor to which the sixth data is to be written does not exceed a verify high voltage, 
 the fifth condition is that a verify low voltage of the sixth data is not determined as being exceeded in an immediately preceding program loop, and 
 the sixth condition is that a number of memory cell transistors that have passed a verify of the seventh data is equal to or greater than a second number in a current program loop. 
 
     
     
       17. The device of  claim 16 , wherein
 the sixth state is higher than the seventh state. 
 
     
     
       18. The device of  claim 1 , wherein
 the states include an eighth state, and a memory cell transistor whose threshold voltage is included in the eighth state stores eighth data, 
 where the eighth state is a state in which a program operation and a verify operation of a one-state preceding state are not executed in a write operation, the controller is configured to perform a verify operation of the eighth data such that: 
 a determination is made as to whether or not a threshold voltage of a memory cell transistor to which the eighth data is to be written exceeds a verify low voltage of the eighth data, while the verify low voltage of the eighth data is being applied to the word line; and 
 a determination is made as to whether or not a threshold voltage of the memory cell transistor to which the eighth data is to be written exceeds a verify high voltage of the eighth data, while the verify high voltage of the eighth data is being applied to the word line. 
 
     
     
       19. A semiconductor memory device comprising:
 a plurality of memory cell transistors each storing a plurality of bits of data, each of threshold voltages of the memory cell transistors being included in one of a plurality of states, the states including a first state, and a memory cell transistor whose threshold voltage is included in the first state storing first data; 
 a word line coupled to the memory cell transistors; 
 a plurality of bit lines coupled to the memory cell transistors, respectively; and 
 a plurality of sense circuits coupled to the bit lines, respectively, each of the sense circuits including a sense node, and each of the sense circuits determining a threshold voltage of a memory cell transistor, based on a voltage of the sense node; and 
 a controller configured to perform a write operation that includes repetition of a program loop including a program operation and a verify operation, 
 wherein 
 a verify low voltage and a verify high voltage are set for each of the states, 
 in a verify operation of the first data, the controller
 charges each of the sense nodes of the sense circuits while a first voltage intermediate between a verify low voltage of the first data and a verify high voltage of the first data is being applied to the word line, and first charges each of the sense nodes of the sense circuits and then discharges each of the sense nodes in a second time longer than the first time while the verify high voltage of the first data is being applied to the word line, and 
 
 a sense circuit coupled to a memory cell transistor to which the first data is to be written determines whether or not a threshold voltage of the memory cell transistor to which the first data is to be written exceeds the verify low voltage of the first data while the first voltage is being applied to the word line, and determines whether or not the threshold voltage of the memory cell transistor to which the first data is to be written exceeds the verify high voltage of the first data. 
 
     
     
       20. The device of  claim 19 , wherein
 in the verify operation, for each state of a write target, the controller is configured to: 
 set a memory cell transistor determined to have a threshold voltage equal to or lower than a verify low voltage, as a first program target; 
 set a memory cell transistor determined to have a threshold voltage exceeding the verify low voltage and being equal to or lower than a verify high voltage, as a second program target; and 
 set a memory cell transistor determined to have a threshold voltage exceeding the verify high voltage as program-inhibit, and 
 while a program voltage is being applied to the word line in the program operation, the controller is configured to: 
 apply a first voltage to a bit line coupled to a memory cell transistor as the first program target; 
 apply a second voltage higher than the first voltage to a bit line coupled to a memory cell transistor set as the second program target; and 
 apply a third voltage higher than the second voltage to a memory cell transistor set as program-inhibit.