Host-assisted IO service levels utilizing false-positive signaling

Abstract

An apparatus comprises at least one processing device. The at least one processing device is configured to identify at least one logical storage device that has a first service level objective and is exhibiting a deficiency in one or more performance metrics, to identify one or more additional logical storage devices each having a second service level objective lower than the first service level objective and not exhibiting a deficiency in the one or more performance metrics, to generate at least one false-positive signal specifying the one or more additional logical storage devices as each exhibiting a deficiency in the one or more performance metrics, and to provide the at least one false-positive signal to at least one host device. The at least one host device is configured to respond to the at least one false-positive signal by throttling input-output operations for the one or more additional logical storage devices.

What is claimed is: 
     
       1. An apparatus comprising:
 at least one processing device comprising a processor coupled to a memory; 
 where the at least one processing device is configured: 
 to identify at least one logical storage device that has a first service level objective and is exhibiting a deficiency in one or more performance metrics; 
 to identify one or more additional logical storage devices each having a second service level objective lower than the first service level objective and not exhibiting a deficiency in the one or more performance metrics; 
 to generate at least one false-positive signal specifying the one or more additional logical storage devices as each exhibiting a deficiency in the one or more performance metrics; and 
 to provide the at least one false-positive signal to at least one host device; 
 wherein the at least one host device is configured to respond to the at least one false-positive signal by throttling input-output operations for the one or more additional logical storage devices. 
 
     
     
       2. The apparatus of  claim 1  wherein the at least one processing device is implemented in a storage system that is configured to communicate with the at least one host device over at least one network. 
     
     
       3. The apparatus of  claim 2  wherein the first service level objective comprises a highest one of a plurality of service level objectives supported by the storage system. 
     
     
       4. The apparatus of  claim 2  wherein the second service level objective comprises a lowest one of a plurality of service level objectives supported by the storage system. 
     
     
       5. The apparatus of  claim 2  wherein the storage system communicates with the at least one host device over the at least one network utilizing a designated storage access protocol that supports a predictable latency mode. 
     
     
       6. The apparatus of  claim 1  wherein the one or more performance metrics comprise at least a response time metric for input-output operations directed to at least one of the logical storage devices by the at least one host device. 
     
     
       7. The apparatus of  claim 1  wherein the at least one false-positive signal is generated in accordance with a signaling mechanism of a predictable latency mode of a designated storage access protocol. 
     
     
       8. The apparatus of  claim 7  wherein the at least one false-positive signal comprises at least one predictable latency warning event of the predictable latency mode. 
     
     
       9. The apparatus of  claim 7  wherein the at least one false-positive signal comprises at least one of a deterministic window reads warning event and a deterministic window writes warning event of the predictable latency mode. 
     
     
       10. The apparatus of  claim 7  wherein the at least one false-positive signal is generated even though values of the one or more performance metrics for respective ones of the one or more additional logical storage devices each fail to satisfy at least one specified threshold for generation of a predictable latency warning event in the predictable latency mode. 
     
     
       11. The apparatus of  claim 1  wherein the at least one host device is configured to respond to the at least one false-positive signal by increasing a queuing time in one or more queues of the at least one host device for each of one or more input-output operations directed to the one or more additional logical storage devices. 
     
     
       12. The apparatus of  claim 1  wherein the at least one false-positive signal is provided to the at least one host device in at least one log page accessible to the at least one host device. 
     
     
       13. The apparatus of  claim 1  wherein the at least one false-positive signal serves to mark each of the one or more additional logical storage devices for de-prioritization by the at least one host device. 
     
     
       14. The apparatus of  claim 1  wherein the at least one false-positive signal is generated for only reads of the one or more additional logical storage devices or for only writes of the one or more additional logical storage devices. 
     
     
       15. A computer program product comprising a non-transitory processor-readable storage medium having stored therein program code of one or more software programs, wherein the program code, when executed by at least one processing device comprising a processor coupled to a memory, causes the processing device:
 to identify at least one logical storage device that has a first service level objective and is exhibiting a deficiency in one or more performance metrics; 
 to identify one or more additional logical storage devices each having a second service level objective lower than the first service level objective and not exhibiting a deficiency in the one or more performance metrics; 
 to generate at least one false-positive signal specifying the one or more additional logical storage devices as each exhibiting a deficiency in the one or more performance metrics; and 
 to provide the at least one false-positive signal to at least one host device; 
 wherein the at least one host device is configured to respond to the at least one false-positive signal by throttling input-output operations for the one or more additional logical storage devices. 
 
     
     
       16. The computer program product of  claim 15  wherein the at least one false-positive signal is generated in accordance with a signaling mechanism of a predictable latency mode of a designated storage access protocol. 
     
     
       17. The computer program product of  claim 16  wherein the at least one false-positive signal comprises at least one of a deterministic window reads warning event and a deterministic window writes warning event of the predictable latency mode. 
     
     
       18. A method comprising:
 identifying at least one logical storage device that has a first service level objective and is exhibiting a deficiency in one or more performance metrics; 
 identifying one or more additional logical storage devices each having a second service level objective lower than the first service level objective and not exhibiting a deficiency in the one or more performance metrics; 
 generating at least one false-positive signal specifying the one or more additional logical storage devices as each exhibiting a deficiency in the one or more performance metrics; and 
 providing the at least one false-positive signal to at least one host device; 
 wherein the at least one host device is configured to respond to the at least one false-positive signal by throttling input-output operations for the one or more additional logical storage devices; 
 wherein the method is performed by at least one processing device comprising a processor coupled to a memory. 
 
     
     
       19. The method of  claim 18  wherein the at least one false-positive signal is generated in accordance with a signaling mechanism of a predictable latency mode of a designated storage access protocol. 
     
     
       20. The method of  claim 19  wherein the at least one false-positive signal comprises at least one of a deterministic window reads warning event and a deterministic window writes warning event of the predictable latency mode.