US11882690B2ActiveUtilityA1

Semiconductor structure having tapered bit line

Assignee: NANYA TECHNOLOGY CORPPriority: Jun 10, 2022Filed: Jun 10, 2022Granted: Jan 23, 2024
Est. expiryJun 10, 2042(~15.9 yrs left)· nominal 20-yr term from priority
H10W 20/039H10B 12/482H01L 21/76852H10B 12/485H10B 12/488
61
PatentIndex Score
0
Cited by
4
References
19
Claims

Abstract

The present disclosure provides a semiconductor structure having a bit line with a tapered configuration. The semiconductor structure includes: a substrate; a bit line structure, disposed over the substrate, wherein the bit line structure includes a cylindrical portion and a step portion above the cylindrical portion; a polysilicon layer, disposed over the substrate and around the bit line structure; and a landing pad, disposed over the polysilicon layer and the step portion.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A semiconductor structure, comprising:
 a substrate; 
 a bit line structure, disposed over the substrate, wherein the bit line structure includes a cylindrical portion and a step portion above the cylindrical portion; 
 a polysilicon layer, disposed over the substrate and around the bit line structure; and 
 a landing pad, disposed over the polysilicon layer and the step portion. 
 
     
     
       2. The semiconductor structure of  claim 1 , wherein a top surface of the step portion is a top surface of the bit line structure. 
     
     
       3. The semiconductor structure of  claim 1 , wherein the step portion is entirely above the polysilicon layer. 
     
     
       4. The semiconductor structure of  claim 1 , further comprising:
 a spacer, disposed between the polysilicon layer and the bit line structure, wherein the spacer surrounds the cylindrical portion of the bit line structure. 
 
     
     
       5. The semiconductor structure of  claim 4 , wherein the spacer is a multi-layer structure, and includes nitride and oxide. 
     
     
       6. The semiconductor structure of  claim 4 , wherein the spacer covers an entirety of the cylindrical portion of the bit line structure. 
     
     
       7. The semiconductor structure of  claim 4 , wherein a top surface of the spacer is above a top surface of the polysilicon layer. 
     
     
       8. The semiconductor structure of  claim 1 , wherein the step portion has differing widths along a height of the bit line structure. 
     
     
       9. The semiconductor structure of  claim 1 , wherein the bit line structure includes a conductive layer under a top surface of the polysilicon layer. 
     
     
       10. A semiconductor structure, comprising:
 a substrate; 
 a bit line structure, disposed on the substrate and extending in a first direction; and 
 a polysilicon layer, disposed around a lower portion of the bit line structure, wherein an upper portion of the bit line structure is tapered from the lower portion toward a top surface of the bit line structure. 
 
     
     
       11. The semiconductor structure of  claim 10 , further comprising:
 a metal layer, disposed over the polysilicon layer and partially covering the upper portion of the bit line structure. 
 
     
     
       12. The semiconductor structure of  claim 11 , wherein the metal layer includes an opening exposing a portion of the upper portion of the bit line structure. 
     
     
       13. The semiconductor structure of  claim 10 , further comprising:
 a word line structure, disposed on the substrate and extending in a second direction different from the first direction. 
 
     
     
       14. The semiconductor structure of  claim 13 , wherein the polysilicon layer surrounds a lower portion of the word line structure. 
     
     
       15. The semiconductor structure of  claim 13 , wherein the word line structure includes an upper portion tapered from the top surface of the polysilicon layer. 
     
     
       16. The semiconductor structure of  claim 10 , further comprising:
 a spacer, disposed on a sidewall of the bit line structure and surrounding the lower portion of the bit line structure. 
 
     
     
       17. The semiconductor structure of  claim 16 , wherein the spacer protrudes from the polysilicon layer. 
     
     
       18. The semiconductor structure of  claim 16 , wherein a portion of the spacer is exposed through a metal layer disposed over the bit line structure. 
     
     
       19. The semiconductor structure of  claim 10 , wherein the lower portion of the bit line structure protrudes from the top surface of the polysilicon layer.

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