Method and device for testing system-on-chip, electronic device using method, and computer readable storage medium

Abstract

A method for testing systems on a chip during manufacture obtains basic function information of intellectual property cores and relevant information of network on chip and generates one or more test names according to the basic function information, and the relevant information of the network on chip. The method invokes a pre-prepared integral script to construct a running environment configured to invoke basic function scripts of to-be-tested intellectual property cores one by one, according to each of the test names which are generated. The method also generates the results of testing. A related electronic device and a non-transitory storage medium are also disclosed.

What is claimed is: 
     
       1. A method for applying tests comprising:
 obtaining basic function information of a plurality of intellectual property cores and relevant information of a network on chip; 
 generating one or more test names according to the basic function information of the intellectual property cores and the relevant information of the network on chip; 
 invoking a pre-written integral script to construct a running environment configured to invoke a plurality of pre-written basic function scripts of to-be-tested intellectual property cores one by one, according to each of the one or more test names which are generated; and 
 generating results of testing; 
 wherein a method of obtaining the basic function information of a plurality of intellectual property cores and the relevant information of the network on chip comprises: 
 obtaining the basic function information of the intellectual property cores and a data transmission path in the network on chip; 
 wherein a method of generating the one or more test names according to the basic function information of the intellectual property cores and the relevant information of the network on chip comprises: 
 generating the one or more test names according to the basic function information of the intellectual property cores and the data transmission path in the network on chip, each of the one or more test names comprising a to-be-tested intellectual property core which executes a data writing operation, a to-be-tested intellectual property core which executes a data reading operation, a to-be-verified and to-be-tested intellectual property core, and one or more manners of data transmission between the to-be-tested intellectual property cores. 
 
     
     
       2. The method according to  claim 1 , wherein a method of generating the one or more test names according to the basic function information of the intellectual property cores and the relevant information of the network on chip comprises:
 generating the one or more test names according to the basic function information of the intellectual property cores and the relevant information of the network on chip, each of the one or more test names comprising a relationship between each of the to-be-tested intellectual property cores; 
 wherein a method of invoking the pre-written integral script to construct the running environment configured to invoke the pre-written basic function scripts of to-be-tested intellectual property cores one by one, according to each of the one or more test names which are generated comprises: 
 invoking the pre-written integral script to construct the running environment configured to invoke each of the pre-written basic function scripts of each of the to-be-tested intellectual property cores in the one or more test names one by one, according to each of the one or more test names which are generated. 
 
     
     
       3. The method according to  claim 2 , wherein:
 a method of generating the one or more test names according to the basic function information of the intellectual property cores and the relevant information of the network on chip, each of the one or more test names comprising the relationship between each of the to-be-tested intellectual property cores comprises: 
 generating the one or more test names according to the basic function information of the intellectual property cores and the data transmission path in the network on chip, each of the one or more test names comprising the relationship of a data transmission between each of the to-be-tested intellectual property cores. 
 
     
     
       4. The method according to  claim 2 , wherein:
 before generating the one or more test names according to the basic function information of the intellectual property cores and the relevant information of the network on chip, each of the one or more test names comprising the relationship between each of the to-be-tested intellectual property cores, the method further comprises: 
 identifying the information of each of the to-be-tested intellectual property cores in the to-be-tested system-on-chip; and wherein: 
 a method of generating the one or more test names according to the basic function information of the intellectual property cores and the relevant information of the network on chip, each of the one or more test names comprising the relationship between each of the to-be-tested intellectual property cores comprises: 
 generating the one or more test names according to the basic function information of the intellectual property cores, the relevant information of the network on chip, and the information of each of the to-be-tested intellectual property cores, each of the one or more test names comprising the relationship between each of the to-be-tested intellectual property cores. 
 
     
     
       5. The method according to  claim 1 , wherein the to-be-verified and to-be-tested intellectual property core comprises a storage unit. 
     
     
       6. The method according to  claim 1  further comprising:
 generating a coverage of all of the to-be-tested intellectual property cores according to the results of testing. 
 
     
     
       7. An electronic device comprising:
 a storage device; 
 at least one processor; and 
 the storage device storing one or more programs, which when executed by the at least one processor, cause the at least one processor to: 
 obtain basic function information of a plurality of intellectual property cores and relevant information of a network on chip; 
 generate one or more test names according to the basic function information of the intellectual property cores and the relevant information of the network on chip; 
 invoke a pre-written integral script to construct a running environment configured to invoke a plurality of pre-written basic function scripts of to-be-tested intellectual property cores one by one, according to each of the one or more test names which are generated; 
 generate results of testing; 
 further causing the at least one processor to: 
 obtain the basic function information of the intellectual property cores and a data transmission path in the network on chip; 
 generate the one or more test names according to the basic function information of the intellectual property cores and the data transmission path in the network on chip, each of the one or more test names comprising a to-be-tested intellectual property core which executes a data writing operation, a to-be-tested intellectual property core which executes a data reading operation, a to-be-verified and to-be-tested intellectual property core, and one or more manners of data transmission between the to-be-tested intellectual property cores. 
 
     
     
       8. The electronic device according to  claim 7 , further causing the at least one processor to:
 generate the one or more test names according to the basic function information of the intellectual property cores and the relevant information of the network on chip, each of the one or more test names comprising a relationship between each of the to-be-tested intellectual property cores; 
 invoke the pre-written integral script to construct the running environment configured to invoke each of the pre-written basic function scripts of each of the to-be-tested intellectual property cores in the one or more test names one by one, according to each of the one or more test names which are generated. 
 
     
     
       9. The electronic device according to  claim 8 , further causing the at least one processor to:
 generate the one or more test names according to the basic function information of the intellectual property cores and the data transmission path in the network on chip, each of the one or more test names comprising the relationship of a data transmission between each of the to-be-tested intellectual property cores. 
 
     
     
       10. The electronic device according to  claim 8 , further causing the at least one processor to:
 identify the information of each of the to-be-tested intellectual property cores in the to-be-tested system-on-chip; 
 generate the one or more test names according to the basic function information of the intellectual property cores, the relevant information of the network on chip, and the information of each of the to-be-tested intellectual property cores, each of the one or more test names comprising the relationship between each of the to-be-tested intellectual property cores. 
 
     
     
       11. The electronic device according to  claim 7 , wherein the to-be-verified and to-be-tested intellectual property core comprises a storage unit. 
     
     
       12. The electronic device according to  claim 7 , further causing the at least one processor to:
 generate a coverage of all of the to-be-tested intellectual property cores according to the results of testing. 
 
     
     
       13. A non-transitory storage medium storing a set of commands, when the commands being executed by at least one processor of an electronic device, causing the at least one processor to:
 obtain basic function information of a plurality of intellectual property cores and relevant information of a network on chip; 
 generate one or more test names according to the basic function information of the intellectual property cores and the relevant information of the network on chip; 
 invoke a pre-written integral script to construct a running environment configured to invoke a plurality of pre-written basic function scripts of to-be-tested intellectual property cores one by one, according to each of the one or more test names which are generated; 
 generate results of testing; 
 further causing the at least one processor to: 
 obtain the basic function information of the intellectual property cores and a data transmission path in the network on chip; 
 generate the one or more test names according to the basic function information of the intellectual property cores and the data transmission path in the network on chip, each of the one or more test names comprising a to-be-tested intellectual property core which executes a data writing operation, a to-be-tested intellectual property core which executes a data reading operation, a to-be-verified and to-be-tested intellectual property core, and one or more manners of data transmission between the to-be-tested intellectual property cores. 
 
     
     
       14. The non-transitory storage medium according to  claim 13 , further causing the at least one processor to:
 generate the one or more test names according to the basic function information of the intellectual property cores and the relevant information of the network on chip, each of the one or more test names comprising a relationship between each of the to-be-tested intellectual property cores; 
 invoke the pre-written integral script to construct the running environment configured to invoke each of the pre-written basic function scripts of each of the to-be-tested intellectual property cores in the one or more test names one by one, according to each of the one or more test names which are generated. 
 
     
     
       15. The non-transitory storage medium according to  claim 14 , further causing the at least one processor to:
 generate the one or more test names according to the basic function information of the intellectual property cores and the data transmission path in the network on chip, each of the one or more test names comprising the relationship of a data transmission between each of the to-be-tested intellectual property cores. 
 
     
     
       16. The non-transitory storage medium according to  claim 14 , further causing the at least one processor to:
 identify the information of each of the to-be-tested intellectual property cores in the to-be-tested system-on-chip; 
 generate the one or more test names according to the basic function information of the intellectual property cores, the relevant information of the network on chip, and the information of each of the to-be-tested intellectual property cores, each of the one or more test names comprising the relationship between each of the to-be-tested intellectual property cores. 
 
     
     
       17. The non-transitory storage medium according to  claim 13 , wherein the to-be-verified and to-be-tested intellectual property core comprises a storage unit.