System for combining digital streams and method for combining digital streams (variants)

Abstract

This invention relates to multichannel signal processing systems using synchronous protocols I2S (Inter-IC Sound Bus) and SPI (Serial Peripheral Bus) for sequenced data exchange, and providing unified synchronization of processed data. The system and method for synchronously multiplexing data streams in the I2S or SPI formats involves transformation of a standard Left/Right Clock (LRCK) sampled pulse signal of the I2S format or a Chip Select (CS) pulse signal of the SPI format into a LRCLt signal comprising a time stamp code and start and end marker codes of the synchronization clock signal, LRCK or CS, respectively. The presence of the marker codes and the time stamp code enables to restore the pulse signal, LRCK or CS, respectively, in the process of data stream program processing and link each discrete sample to the time stamp. The digital stream multiplexing system includes m channel groups for collection of synchronous data in the I2S or SPI synchronous protocol, a clock generator, a host processor and a means of transforming the LRCK or CS signal into the LRCKt signal. The technical effect consists in removal of limitations on a number of fully synchronized data streams in the I2S or SPI formats and, at the same time, simplification of the synchronization system and method and reduction in requirements to hardware resources.

The invention claimed is: 
     
       1. A system for combining digital streams, comprising:
 m groups of channels for collecting synchronous data in the synchronous protocol format, each group of channels including:
 a means for pre-processing analog signals, which has N inputs for processing signals transmitted from N sources of analog signals, and N outputs, 
 N/2 paired analog-to-digital converters (ADC), each having N inputs, a data stream clock synchronization input, a common synchronization input, a frame synchronization input and N/2 outputs, and 
 a main processor with asynchronous interface, which has N/2 inputs and a data recording input, 
 wherein the N outputs of the pre-processing means are connected to N inputs of the N/2 ADCs, and the N/2 ADC outputs are connected to the N/2 inputs of the main processor, 
 
 a clock oscillator having:
 a control input, a first output forming a clock signal for synchronization of a BCLK data stream, a second output forming a MCLK service signal for common synchronization, and a third output forming a pulse signal of the respective synchronous protocol, 
 
 a host processor having:
 a control bus and 
 at least two asynchronous interfaces to which said at least two groups of channels are connected respectively, and 
 
 a means of transforming the pulse signal of the respective synchronous protocol into a LRCKt signal, the means comprising:
 a circuit for selecting an edge and a fall of the pulse signal, 
 a shift register having a data shift input, 
 a first “AND” circuit and a second “AND” circuit, each of them having a first control input, a second control input, and a digital output, and 
 a binary counter having a count input and digital outputs, 
 
 wherein the control input of the clock oscillator is connected to the control bus of the host processor, 
 the first output of the clock oscillator is connected to the ADC data stream clock synchronization input, the data recording input of the main processors, and the data transfer input of the shift register, 
 the second output of the clock oscillator is connected to the ADC common synchronization inputs, 
 the third output of the clock oscillator is connected to the ADC frame synchronization input, the input of the circuit for selecting an edge and a fall of the pulse signal of the respective synchronous protocol, the first control input of the first “AND” circuit and the first control input of the second “AND” circuit, 
 the second control input of the first “AND” circuit and the second control input of the second “AND” circuit are configured to preliminary set fixed codes of the Nstart marker and the Nend marker of the pulse signal of the respective synchronous protocol, 
 the digital output of the first “AND” circuit is connected to low-order bits of the shift register, the digital output of the second “AND” circuit is connected to high-order bits of the shift register, and the digital output of the binary counter is connected to intermediate-order bits of the shift register, and 
 the count input of the binary counter and the recording input of the shift register are connected to the output of the circuit for selecting an edge and a fall edge of the pulse signal of the respective synchronous protocol. 
 
     
     
       2. The system of  claim 1 , wherein said synchronous protocol is the I2S protocol, and said pulse signal is the Left/Right Clock (LRCK) sampled clock signal of the I2S format. 
     
     
       3. The system of  claim 1 , wherein said synchronous protocol is the SPI protocol, and said pulse signal is the Chip Select (CS) chip selection signal of the SPI format. 
     
     
       4. A method for combining digital streams of the I2S format, wherein:
 an analog signal array having a mN volume is received, which signals are transmitted from the m groups of channels for collecting synchronous data in the synchronous protocol format, each group of channels including N analog signals; 
 said analog signal array is pre-processed; 
 the processed analog signal array is forwarded to the paired ADCs and is transformed into a serial digital code in the I2S format together with formation of N/2 serial data digital streams; 
 said serial data digital streams are forwarded to the inputs of the main processor and are recorded at the edge of pulses of the BCLK data stream synchronization clock signal transmitted from the clock oscillator; 
 a time stamp is embedded into the Left/Right Clock (LRCK) sampled pulse signal of the I2S format, wherein:
 the LRCK signal is transformed into a LRCKt signal, the time stamp code being generated by the binary counter, the Nt time stamp code is recorded into the shift register at the edges of the pulses, and a change of the binary counter state is fixed at the falls of the pulse, and the markers Nstart and Nend of the LRCK pulse signal are recorded into the shift register simultaneously with the recording of the Nt time stamp code, but only at the times when the LRCK pulse signal has a high level; and 
 
 after recording the Nstart, Nt and Nend codes into the register, a sequence of the LRCKt complex clock signal pulses is formed under the action of the BCLK clock signal pulses. 
 
     
     
       5. The method of  claim 4 , characterized in that the pre-processing of an analog signal array comprises amplification, filtration and transformation, depending on properties specific to analog signals. 
     
     
       6. A method for combining digital streams of the SPI format, wherein:
 an analog signal array having a mN volume is received, which signals are transmitted from the m groups of channels for collecting synchronous data in the synchronous protocol format, each group of channels including N analog signals; 
 said analog signal array is pre-processed; 
 the processed analog signal array is forwarded to the paired ADCs and is transformed into a serial digital code in the SPI format together with formation of N/2 serial data digital streams; 
 said serial data digital streams are forwarded to the inputs of the main processor and are recorded at the edges of pulses of the BCLK data stream synchronization clock signal transmitted from the clock oscillator; 
 a time stamp is embedded into the Chip Select (CS) pulse signal of the SPI format, wherein:
 the CS signal is transformed into a LRCKt signal, the time stamp code being generated by the binary counter, the Nt time stamp code is recorded into the shift register at the edges of the pulses, and a change of the binary counter state is fixed at the falls of the pulses, and the markers Nstart and Nend of the CS signal are recorded into the shift register simultaneously with the recording of the Nt time stamp code, but only at the times when the CS signal has a high level; and 
 
 after recording the Nstart, Nt and Nend codes into the register, a sequence of the LRCKt complex clock signal pulses is formed under the action of the BCLK clock signal pulses. 
 
     
     
       7. The method of  claim 6 , characterized in that the pre-processing of an analog signal array comprises amplification, filtration and transformation, depending on properties specific to analog signals.