Asynchronous circuit with multi-input threshold gate logic and 1-input threshold gate

Abstract

Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1 V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.

We claim: 
     
       1. An apparatus comprising:
 a first threshold gate to receive a first set of inputs and to generate a first output in accordance with a first threshold of the first threshold gate and in accordance with logic values of the first set of inputs; 
 a first transistor having a first gate terminal coupled to the first output; 
 a second threshold gate to receive a second set of inputs and to generate a second output in accordance with a second threshold of the second threshold gate and in accordance with logic values of the second set of inputs; 
 a second transistor having a second gate terminal coupled to the second output, wherein the first transistor and the second transistor are coupled in series at a common node; 
 a third threshold gate coupled to the common node, wherein the third threshold gate comprises: 
 a capacitor having a first terminal coupled to the common node, and a second terminal coupled to a third output; and 
 a third transistor coupled to the third output, wherein the third transistor is controllable by a first control. 
 
     
     
       2. The apparatus of  claim 1 , wherein the third threshold gate is to preserve a logic value when the first transistor and the second transistor are off. 
     
     
       3. The apparatus of  claim 1 , wherein the third threshold gate is a 1-input capacitive circuit with a threshold of 1. 
     
     
       4. The apparatus of  claim 1 , wherein the third threshold gate comprises a fourth transistor coupled to the third output, wherein the fourth transistor is controllable by a second control, wherein the third transistor is a p-type transistor, and wherein the fourth transistor is an n-type transistor. 
     
     
       5. The apparatus of  claim 1 , wherein the capacitor comprises a paraelectric material or a ferroelectric material. 
     
     
       6. The apparatus of  claim 1 , wherein the first threshold gate, the first transistor, the second threshold gate, and the second transistor are part of an asynchronous circuit. 
     
     
       7. The apparatus of  claim 1 , wherein the first transistor is a p-type transistor, and wherein the second transistor is an n-type transistor. 
     
     
       8. The apparatus of  claim 1 , wherein the third threshold gate comprises:
 a first capacitor having a third terminal coupled to receive a first input of the first set of inputs, the first capacitor having a fourth terminal coupled to a first summing node; and 
 a second capacitor having a fifth terminal coupled to receive a second input of the first set of inputs, the second capacitor having a sixth terminal coupled to the first summing node. 
 
     
     
       9. The apparatus of  claim 8 , wherein the first summing node is coupled to the first gate terminal of the first transistor. 
     
     
       10. The apparatus of  claim 8 , wherein the first capacitor and the second capacitor have linear dielectric. 
     
     
       11. The apparatus of  claim 1 , wherein the second threshold gate comprises:
 a first capacitor having a third terminal coupled to receive a first input of the second set of inputs, the first capacitor having a fourth terminal coupled to a second summing node; and 
 a second capacitor having a fifth terminal coupled to receive a second input of the second set of inputs, the second capacitor having a sixth terminal coupled to the second summing node. 
 
     
     
       12. The apparatus of  claim 11 , wherein the second summing node is coupled to the second gate terminal of the second transistor. 
     
     
       13. The apparatus of  claim 11 , wherein the first capacitor and the second capacitor have linear dielectric or non-linear polar dielectric. 
     
     
       14. An apparatus comprising:
 a first transistor of a first conductivity type; 
 a second transistor of a second conductivity type, wherein the second transistor is coupled is series with the first transistor, wherein the first conductivity type is different from the second conductivity type; 
 a first threshold gate comprising a first capacitive input circuit, wherein the first threshold gate is to drive the first transistor; 
 a second threshold gate comprising a second capacitive input circuit, wherein the second threshold gate is to drive the second transistor; and 
 a third threshold gate coupled to the first transistor and the second transistor, wherein the first threshold gate and the second threshold gate have adjustable thresholds. 
 
     
     
       15. The apparatus of  claim 14 , wherein the second capacitive input circuit includes one or more capacitors which include one of: a linear dielectric, a non-linear dielectric, a paraelectric dielectric, or a ferroelectric dielectric. 
     
     
       16. The apparatus of  claim 14 , wherein the third threshold gate has a threshold of 1. 
     
     
       17. The apparatus of  claim 14 , wherein the first capacitive input circuit includes capacitors which comprises one of: a linear dielectric, a non-linear dielectric, a paraelectric dielectric, or a ferroelectric dielectric. 
     
     
       18. A system comprising:
 a memory circuitry to store one or more instructions; 
 a processor circuitry coupled to the memory circuitry; and 
 a communication interface coupled to the processor circuitry, wherein the processor circuitry is to execute the one or more instructions, wherein the processor circuitry includes an asynchronous circuitry, and wherein the asynchronous circuitry includes: 
 a first transistor of a first conductivity type; 
 a second transistor of a second conductivity type, wherein the second transistor is coupled is series with the first transistor, wherein the first conductivity type is different from the second conductivity type; 
 a first threshold gate comprising a first capacitive input circuit, wherein the first threshold gate is to drive the first transistor; 
 a second threshold gate comprising a second capacitive input circuit, wherein the second threshold gate is to drive the second transistor; and 
 a third threshold gate coupled to the first transistor and the second transistor, wherein the first threshold gate and the second threshold gate have adjustable thresholds. 
 
     
     
       19. The system of  claim 18 , wherein the third threshold gate has a threshold of 1.