Wireless BMS host time synchronization mechanism

Abstract

Low-cost time synchronization associated wireless Battery Management System (BMS) and a host controller are described herein. The time synchronization techniques described herein are low-cost because of the use of existing communicating lines without using adding additional dedicated lines or wires for synchronization. Moreover, the time synchronization techniques described herein may be implemented without complex circuitry.

What is claimed is: 
     
       1. A method to synchronize timing between a host controller and a wireless manager, the method comprising:
 detecting, at the host controller, a timing mismatch between the host controller and the wireless manager; and 
 in response to detecting the timing mismatch:
 transmitting a unique word including a fixed pattern of bits to the wireless manager using a common data line in a communication interface; 
 obtaining a master timestamp from a clock at the host controller at an instant a specified bit of the fixed pattern of bits of the unique word is transmitted; and 
 transmitting the master timestamp to the wireless manager using the common data line in the communication interface. 
 
 
     
     
       2. The method of  claim 1 , wherein the specified bit is a last bit of the unique word. 
     
     
       3. The method of  claim 1 , wherein the communication interface includes a serial peripheral interface (SPI), and wherein the unique word is transmitted over a Master Output Slave Input (MOSI) line of the SPI. 
     
     
       4. The method of  claim 3 , wherein the communication interface includes an isolated SPI. 
     
     
       5. The method of  claim 1 , further comprising:
 detecting a buffer overflow state, the buffer overflow state indicating the timing mismatch. 
 
     
     
       6. The method of  claim 1 , further comprising:
 detecting a buffer underflow state, the buffer underflow state indicating the timing mismatch. 
 
     
     
       7. A system, comprising:
 a host controller comprising a host clock; 
 a wireless manager comprising a local clock; 
 a communication interface between the host controller and the wireless manager, wherein the host controller including a circuit configured to in response to detecting a timing mismatch between the host and local clocks:
 transmitting a unique word including a fixed pattern of bits to the wireless manager using a common data line in the communication interface; 
 obtaining a master timestamp from the host clock at an instant a specified bit of the fixed pattern of bits of the unique word is transmitted; and 
 transmitting the master timestamp to the wireless manager using the common data line in the communication interface; 
 
 the wireless manager including a circuit configured to:
 receiving the unique word from the host controller; 
 obtaining a slave timestamp from the local clock at the wireless manager at an instant the specified bit of the unique word is received; 
 receiving the master timestamp from the host controller; 
 based on the master timestamp and slave timestamp, adjusting timing of the local clock. 
 
 
     
     
       8. The system of  claim 7 , wherein the specified bit is a last bit of the unique word. 
     
     
       9. The system of  claim 7 , wherein the communication interface includes a serial peripheral interface (SPI), and wherein the unique word is transmitted over a Master Output Slave Input (MOSI) line of the SPI. 
     
     
       10. A non-transitory machine-readable medium embodying instructions that, when executed by a machine, cause the machine to perform operations comprising:
 detecting, at a host controller, a timing mismatch between the host controller and a wireless manager; and 
 in response to detecting the timing mismatch:
 transmitting a unique word including a fixed pattern of bits to the wireless manager using a common data line in a communication interface; 
 obtaining a master timestamp from a clock at the host controller at an instant a specified bit of the fixed pattern of bits of the unique word is transmitted; and 
 transmitting the master timestamp to the wireless manager using the common data line in the communication interface. 
 
 
     
     
       11. The non-transitory machine-readable medium of  claim 10 , wherein the specified bit is a last bit of the unique word. 
     
     
       12. The non-transitory machine-readable medium of  claim 10 , wherein the communication interface includes a serial peripheral interface (SPI), and wherein the unique word is transmitted over a Master Output Slave Input (MOSI) line of the SPI. 
     
     
       13. The non-transitory machine-readable medium of  claim 12 , wherein the communication interface includes an isolated SPI. 
     
     
       14. The non-transitory machine-readable medium of  claim 10 , wherein the operations further comprise:
 detecting a buffer overflow state, the buffer overflow state indicating the timing mismatch. 
 
     
     
       15. The non-transitory machine-readable medium of  claim 10 , wherein the operations further comprise:
 detecting a buffer underflow state, the buffer underflow state indicating the timing mismatch.