Semiconductor apparatus having a silicide between two devices

Abstract

Aspects of the present disclosure provide 3D semiconductor apparatus and a method for fabricating the same. The 3D semiconductor apparatus can include a first semiconductor device including first S/D regions, a first gate region sandwiched by the first S/D regions, and a first channel surrounded by the first S/D regions and the first gate region; a second semiconductor device stacked on the first semiconductor device that includes second S/D regions, a second gate region sandwiched by the second S/D regions, and a second channel surrounded by the second S/D regions and the second gate region and formed vertically in-situ on the first channel; and silicide formed between the first and second semiconductor devices where the first and second channels interface and coupled to an upper one of the first S/D regions of the first semiconductor device and a lower one of the second S/D regions of the second semiconductor device.

What is claimed is: 
     
       1. A semiconductor apparatus, comprising:
 a first semiconductor device that includes first S/D regions, a first gate region sandwiched by the first S/D regions, and a first channel surrounded by one of the first S/D regions and the first gate region; 
 a second semiconductor device stacked on the first semiconductor device that includes second S/D regions, a second gate region sandwiched by the second S/D regions, and a second channel surrounded by the second S/D regions and one of the second gate region and formed vertically in-situ on the first channel; and 
 silicide formed between the first semiconductor device and the second semiconductor device where the first channel interfaces with the second channel and coupled to an upper one of the first S/D regions of the first semiconductor device and a lower one of the second S/D regions of the second semiconductor device. 
 
     
     
       2. The semiconductor apparatus of  claim 1 , wherein the first semiconductor device and the second semiconductor device are of different types. 
     
     
       3. The semiconductor apparatus of  claim 1 , wherein the first gate region includes a first metal material and a second metal material surrounded by the first metal material, and the second gate region includes the first metal material and a third metal material surrounded by the first metal material. 
     
     
       4. The semiconductor apparatus of  claim 3 , wherein the second and third metal materials include a same metal material. 
     
     
       5. The semiconductor apparatus of  claim 1  wherein the first S/D regions comprise and an upper S/D region and a lower S/D region, the upper S/D region surrounds the channel at a side surface of the channel and the lower S/D region contacts a lower surface of the first channel. 
     
     
       6. The semiconductor device of  claim 1  wherein the second S/D region S/D regions comprise and an upper S/D region and a lower S/D region, the lower S/D region surrounds the channel at a side surface of the channel and the upper S/D region contacts an upper surface of the second channel. 
     
     
       7. The semiconductor apparatus of  claim 1  wherein the first S/D regions comprise and a first upper S/D region and a first lower S/D region, the first upper S/D region surrounds the channel at a side surface of the channel and the first lower S/D region contacts a lower surface of the channel; and
 the second S/D regions comprise and a second upper S/D region and a second lower S/D region, the second lower S/D region surrounds the channel at a side surface of the channel and the upper S/D region contacts an upper surface of the channel. 
 
     
     
       8. The semiconductor apparatus of  claim 7  wherein the first upper S/D region and second lower S/D region are a common S/D region that contacts both the first and second channels. 
     
     
       9. The semiconductor apparatus of  claim 8  wherein the first lower S/D region is coupled to a ground, the first and second gates are coupled to a V in  conductive region, and the second channel is coupled to a V out  conductive region and V dd  conductive region, the V out  conductive region separated from the second channel by a high-K dielectric. 
     
     
       10. The semiconductor apparatus of  claim 1  configured to operate as an inverter.