Stacked memory device with paired channels

Abstract

A stacked memory device includes memory dies over a base die. The base die includes separate memory channels to the different dies and external channels that allow an external processor access to the memory channels. The base die allows the external processor to access multiple memory channels using more than one external channel. The base die also allows the external processor to communicate through the memory device via the external channels, bypassing the memory channels internal to the device. This bypass functionality allows the external processor to connect to additional stacked memory devices.

The invention claimed is: 
     
       1. A stacked memory device comprising:
 at least one memory die having first addressable memory and second addressable memory; 
 a base die stacked with the memory die, the base die having:
 first internal, intra-stack, command and data connections to the first addressable memory; 
 second internal, intra-stack, command and data connections to the second addressable memory; 
 a first external channel with first external command and data connections; 
 a second external channel with second external command and data connections; and 
 a command and data interface to selectively connect the first external command and data connections to the first internal, intra-stack, command and data connections responsive to a first address signal and to the second internal, intra-stack, command and data connections responsive to a second address signal. 
 
 
     
     
       2. The stacked memory device of  claim 1 , the command and data interface to selectively interconnect the first external command and data connections with the second external command and data connections. 
     
     
       3. The stacked memory device of  claim 1 , wherein the command and data interface includes a bidirectional command link between the command connections of the first external command and data connections with the command connections of the second external command and data connections. 
     
     
       4. The stacked memory device of  claim 1 , wherein the at least one memory die comprises a first memory die with the first addressable memory and a second memory die with the second addressable memory. 
     
     
       5. The stacked memory device of  claim 1 , the base die further comprising a command decoder coupled to the first external channel to decode commands and direct data received on the first external command and data connections. 
     
     
       6. The stacked memory device of  claim 5 , wherein the command decoder is coupled to the second external channel to decode commands and direct data received on the second command and data connections. 
     
     
       7. The stacked memory device of  claim 5 , wherein the command decoder decodes one of the commands on the first external channel to direct the data received on the first external command and data connections to the second command and data connections. 
     
     
       8. The stacked memory device of  claim 5 , further comprising a mode register coupled to the command decoder, the mode register to store a mode value responsive to the commands, the mode value defining connectivity between one of the first and second external command and data connections and one of the first and second internal, intra-stack, command and data connections. 
     
     
       9. The stacked memory device of  claim 1 , further comprising a processing die stacked with the base die and the at least one memory die. 
     
     
       10. The stacked memory device of  claim 9 , wherein the processing die comprises a neural network. 
     
     
       11. A memory system comprising:
 a processing unit having a memory interface to issue commands and communicate data; and 
 a die stack having:
 a first memory die having first addressable memory; 
 a second memory die having second addressable memory; and 
 a base die stacked with the memory die, the base die having:
 a first external channel coupled to the memory interface to receive the commands and communicate the data; 
 a second external channel with second command and data connections; 
 a first internal, intra-stack channel coupled to the first addressable memory; 
 a second internal, intra-stack channel coupled to the second addressable memory; and 
 a command and data interface to selectively connect the first external channel to the first internal, intra-stack channel responsive to a first address signal and to the second internal, intra-stack channel responsive to a second address signal. 
 
 
 
     
     
       12. The memory system of  claim 11 , the processing unit having a second memory interface to issue second commands and communicate second data, the second memory interface coupled to the second external channel to receive the second commands and communicate the second data. 
     
     
       13. The memory system of  claim 11 , the command and data interface to selectively interconnect the first external channel with the second external channel. 
     
     
       14. The memory system of  claim 11 , the command and data interface to selectively interconnect the first external channel to the second external channel. 
     
     
       15. The memory system of  claim 11 , wherein the command and data interface includes a bidirectional command interface and a bidirectional data interface. 
     
     
       16. The memory system of  claim 11 , the base die further comprising a command decoder coupled to the first external channel to decode commands received via the first external channel. 
     
     
       17. The memory system of  claim 16 , wherein the command decoder is coupled to the second external channel to decode second commands received via the second external channel. 
     
     
       18. The memory system of  claim 11 , further comprising a processing die stacked with the base die, the first memory die, and the second memory die. 
     
     
       19. The memory system of  claim 18 , wherein the first memory die and the second memory die are between the base die and the processing die.