Multi-phase clock generator and method thereof

Abstract

A multi-phase clock generator is provided in the application. The multi-phase clock generator includes a first oscillator circuit and a second oscillator circuit. The first oscillator circuit includes a plurality of first delay circuits. The first oscillator circuit receives the first number of multi-phase input clock signals and outputs the second number of first output clock signals, wherein the second number is larger than the first number. The second oscillator circuit is coupled to the first oscillator circuit. The second oscillator circuit includes a plurality of second delay circuits. The second oscillator circuit receives the second number of first output clock signals and outputs the second number of second output clock signals. The number of second delay circuits is less than the number of first delay circuits.

What is claimed is: 
     
       1. A multi-phase clock generator, comprising:
 a first oscillator circuit, comprising a plurality of first delay circuits, wherein the first oscillator circuit receives a first number of multi-phase input clock signals and outputs a second number of first output clock signals, wherein the second number is larger than the first number; and 
 a second oscillator circuit, coupled to the first oscillator circuit and comprising a plurality of second delay circuits, wherein the second oscillator circuit receives the second number of first output clock signals and outputs a second number of second output clock signals, wherein the number of the plurality of the second delay circuits is less than the number of the plurality of the first delay circuits. 
 
     
     
       2. The multi-phase clock generator of  claim 1 , wherein the first oscillator circuit comprises a plurality of first output nodes and the second oscillator circuit comprises a plurality of second output nodes, wherein the first output nodes used to output the second number of first output clock signals are coupled to the respective second output nodes. 
     
     
       3. The multi-phase clock generator of  claim 1 , wherein the number of the plurality of first delay circuits is an odd value. 
     
     
       4. The multi-phase clock generator of  claim 1 , wherein the number of the plurality of first delay circuits is an even value. 
     
     
       5. The multi-phase clock generator of  claim 1 , further comprising:
 a current source array, coupled to the first oscillator circuit and the second oscillator circuit, 
 wherein the current source array provides currents to the first oscillator circuit and the second oscillator circuit to make the first oscillator circuit and the second oscillator circuit being operated in a fixed frequency range. 
 
     
     
       6. The multi-phase clock generator of  claim 5 , further comprising:
 a first automatic adjustment circuit, coupled to the first oscillator circuit and the current source array, 
 wherein the first automatic adjustment circuit receives a feedback signal output by the first oscillator circuit and a reference clock signal, and compares the feedback signal with the reference clock signal to adjust the current output by the current source array. 
 
     
     
       7. The multi-phase clock generator of  claim 6 , wherein the first automatic adjustment circuit further comprises:
 a first counter, receiving the reference clock signal; 
 a second counter, receiving the feedback signal; 
 a logic calculation circuit, coupled to the first counter and the second counter, determining whether a first frequency of the reference clock signal is substantially equal to a second frequency of the feedback signal, wherein the multi-phase input clock signals are substantially the first frequency. 
 
     
     
       8. The multi-phase clock generator of  claim 7 , wherein when the first frequency is different from the second frequency, the logic calculation circuit outputs an adjustment signal to the current source array to adjust the current output by the current source array. 
     
     
       9. The multi-phase clock generator of  claim 6 , wherein when the current is adjusted, the frequency range corresponding to the first oscillator circuit is adjusted accordingly. 
     
     
       10. The multi-phase clock generator of  claim 6 , further comprising:
 a second automatic adjustment circuit, coupled to the second oscillator circuit and the current source array, 
 wherein the second automatic adjustment circuit receives a feedback signal output by the second oscillator circuit and the reference clock signal, and compares the feedback signal with the reference clock signal to adjust the current output by the current source array. 
 
     
     
       11. A multi-phase clock-generating method, applied to a multi-phase clock generator, comprising:
 receiving, by a first oscillator circuit of the multi-phase clock generator, a plurality of multi-phase input clock signals, wherein the first oscillator circuit comprises a plurality of first delay circuits; 
 outputting, by the first oscillator circuit, a plurality of multi-phase first output clock signals based on the plurality of multi-phase input clock signals, wherein a number of the multi-phase first output clock signals is larger than a number of the multi-phase input clock signals; 
 receiving, by a second oscillator circuit of the multi-phase clock generator, the multi-phase first output clock signals, wherein the second oscillator circuit comprises a plurality of second delay circuits; and 
 outputting, by the second oscillator circuit, a plurality of multi-phase second output clock signals, wherein a number of the plurality of second delay circuits is less than a number of the plurality of first delay circuits, and a number of the multi-phase second output clock signals is the same as the number of the multi-phase first output clock signals. 
 
     
     
       12. The multi-phase clock-generating method of  claim 11 , wherein the first oscillator circuit comprises a plurality of first output nodes and the second oscillator circuit comprises a plurality of second output nodes, wherein the first output nodes used to output the second number of first output clock signals are coupled to the respective second output nodes. 
     
     
       13. The multi-phase clock-generating method of  claim 11 , wherein the number of the plurality of first delay circuits is an odd value. 
     
     
       14. The multi-phase clock-generating method of  claim 11 , wherein the number of the plurality of first delay circuits is an even value. 
     
     
       15. The multi-phase clock-generating method of  claim 11 , further comprising:
 providing, by a current source array of the multi-phase clock generator, currents to the first oscillator circuit and the second oscillator circuit to make the first oscillator circuit and the second oscillator circuit being operated in a fixed frequency range. 
 
     
     
       16. The multi-phase clock-generating method of  claim 15 , further comprising:
 receiving, by a first automatic adjustment circuit of the multi-phase clock generator, a feedback signal output by the first oscillator circuit and a reference clock signal; 
 comparing, by the first automatic adjustment circuit, the feedback signal with the reference clock signal to adjust the current output by the current source array. 
 
     
     
       17. The multi-phase clock-generating method of  claim 16 , further comprising:
 determining, by the first automatic adjustment circuit, whether a first frequency of the reference clock signal is substantially equal to a second frequency of the feedback signal, wherein the multi-phase input clock signals are substantially the first frequency. 
 
     
     
       18. The multi-phase clock-generating method of  claim 17 , further comprising:
 when the first frequency is different from the second frequency, outputting, by the first automatic adjustment circuit, an adjustment signal to the current source array to adjust the current output by the current source array. 
 
     
     
       19. The multi-phase clock-generating method of  claim 16 , wherein when the current is adjusted, the frequency range corresponding to the first oscillator circuit is adjusted accordingly. 
     
     
       20. The multi-phase clock-generating method of  claim 16 , further comprising:
 receiving, by a second automatic adjustment circuit of the multi-phase clock generator, a feedback signal output by the second oscillator circuit and the reference clock signal and comparing the feedback signal with the reference clock signal to adjust the current output by the current source array.