Correction of sigma-delta analog-to-digital converters (ADCs) using neural networks

Abstract

Systems and methods for correction of sigma-delta analog-to-digital converters (ADCs) using neural networks are described. In an illustrative, non-limiting embodiment, a device may include: an ADC; a filter coupled to the ADC, where the filter is configured to receive an output from the ADC and to produce a filtered output; and a neural network coupled to the filter, where the neural network is configured to receive the filtered output and to produce a corrected output.

The invention claimed is: 
     
       1. A device, comprising:
 an analog-to-digital converter (ADC); 
 a filter coupled to the ADC, wherein the filter is configured to receive an output from the ADC and to produce a filtered output; and 
 a neural network coupled to the filter, wherein the neural network is configured to receive the filtered output and to produce a corrected output. 
 
     
     
       2. The device of  claim 1 , wherein the ADC comprises a delta-sigma ADC. 
     
     
       3. The device of  claim 1 , wherein the filter is configured to reduce out-of-band frequency content of the output. 
     
     
       4. The device of  claim 1 , wherein the neural network is further configured to receive a Process-Voltage-Temperature (PVT) parameter and to produce the corrected output based, at least in part, upon the PVT parameter. 
     
     
       5. The device of  claim 1 , further comprising:
 a reference ADC configured to receive an analog input provided to the ADC and to produce a target output; and 
 another filter coupled to the reference ADC, wherein the other filter is configured to receive the target output and to produce a filtered target output. 
 
     
     
       6. The device of  claim 5 , wherein to produce the corrected output, the neural network is trained with a difference between corrected outputs and filtered target outputs. 
     
     
       7. The device of  claim 1 , further comprising:
 a delay circuit coupled between the filter and the neural network, wherein the delay circuit is configured to apply a time delay to the filtered output; and 
 another filter coupled between the filter and the delay circuit, wherein the other filter is configured to receive the filtered output and to produce a target output, and wherein the time delay is configured to synchronize the filtered output with the target output. 
 
     
     
       8. The device of  claim 7 , wherein the filter is configured to reduce quantization noise of the output, and wherein the other filter is configured to reduce harmonic distortion of the filtered output. 
     
     
       9. The device of  claim 7 , wherein to produce the corrected output, the neural network is trained with a difference between corrected outputs and target outputs. 
     
     
       10. A device, comprising:
 an analog-to-digital converter (ADC); 
 a filter coupled to the ADC, wherein the filter is configured to receive an output from the ADC and to produce a filtered output; and 
 a neural network coupled to the filter, wherein the neural network is configured to receive the filtered output and to predict an error that, subtracted from the filtered output, produces a corrected output. 
 
     
     
       11. The device of  claim 10 , wherein the ADC comprises a delta-sigma ADC. 
     
     
       12. The device of  claim 10 , wherein the filter is configured to remove out-of-band frequency content of the output. 
     
     
       13. The device of  claim 10 , wherein the neural network is further configured to receive a digital representation of a Process-Voltage-Temperature (PVT) parameter and to predict the error based, at least in part, upon the digital representation of the PVT parameter. 
     
     
       14. The device of  claim 10 , further comprising another filter coupled to a digital representation of a reference ADC output, wherein the other filter is configured to receive the digital representation of the reference ADC output and to produce an intermediate output, and wherein the intermediate output subtracted from the filtered output produces a target output. 
     
     
       15. The device of  claim 14 , wherein to predict the error, the neural network is trained with a difference between predicted errors and target outputs. 
     
     
       16. The device of  claim 10 , further comprising:
 a delay circuit coupled between the filter and the neural network, wherein the delay circuit is configured to apply a time delay to the filtered output to produce a delayed, filtered output; and 
 another filter coupled between the filter and the delay circuit, wherein the other filter is configured to receive the filtered output and to produce an intermediate output, wherein the intermediate output subtracted from the delayed, filtered output produces a target output, and wherein the time delay is configured to synchronize the delayed, filtered output with the target output. 
 
     
     
       17. The device of  claim 16 , wherein the filter is configured to reduce quantization noise of the output, and wherein the other filter is configured to reduce harmonic distortion of the filtered output. 
     
     
       18. The device of  claim 16 , wherein to predict the error, the neural network is trained with a difference between predicted errors and target outputs. 
     
     
       19. A method, comprising:
 receiving an analog input at an analog-to-digital converter (ADC); and 
 producing a digital output by the ADC, wherein the ADC is coupled to a neural network via a filter, wherein the filter is configured to reduce out-of-band frequency content of the digital output, and wherein the neural network is configured to produce at least one of: (a) a corrected digital output; or (b) a predicted error. 
 
     
     
       20. The method of  claim 19 , wherein the ADC comprises a delta-sigma ADC.