Video signal processing device, video freeze detecting circuit and method of detecting video freeze

Abstract

A video signal processing device including a video signal dividing unit that divides a video signal into first to k-th division video signals (k is an integer of 2 or more) for each frame; a video change detecting unit that detects, for each of the first to k-th division video signals, whether or not there has occurred a change in the video signal between the frames, and generates first to k-th video change detection signals representing the detection results; and a video no-change determining unit that generates a video no-change signal indicating that there is no change in the video signal when the number of video change detection signals indicating that there is no change among the first to k-th video change detection signals is greater than a predetermined number.

What is claimed is: 
     
       1. A video signal processing device comprising:
 a video signal dividing circuit configured to receive a video signal including a series of N frames and a series of pixel data pieces for each of the N frames, and to divide said video signal into first to k-th division video signals for each of the N frames, wherein N is an integer of 2 or more, and k is an integer of 2 or more; 
 a video change detecting circuit configured to detect whether or not there is a difference in each of said first to k-th division video signals between adjacent frames of the N frames by comparing said first to k-th division video signals in one of the adjacent frames with said first to k-th division video signals in the other of the adjacent frames, respectively, and to generate first to k-th video change detection signals representing respective results of the detection; 
 a video no-change determining circuit configured to generate a video no-change signal indicating that there is no change in said video signal between said adjacent frames of the N frames when regarding a number of video change detection signals indicating that there is no difference among said first to k-th video change detection signals between said adjacent frames of the N frames, the number is greater than a predetermined number L, wherein L is an integer of 1 or more and Lis k or less; and 
 a repetition determining circuit configured to output a freeze detection signal indicating that there is no change in a video based on said video signal when said video no-change signal is repeatedly generated during a period of M frames of the N frames, wherein M is an integer of 2 or more and M is N or less. 
 
     
     
       2. The video signal processing device according to  claim 1 , wherein said video change detecting circuit comprises:
 first to k-th cyclic redundancy check computation circuits configured to individually perform cyclic redundancy check computation on said first to k-th division video signals to compute remainders as first to k-th check values; 
 delay circuits configured to delay said first to k-th check values by one frame period to generate first to k-th delayed check values; and 
 comparison circuits configured to compare said first to k-th check values with said first to k-th delayed check values, respectively, and to generate k signals individually indicating comparison results as said first to k-th video change detection signals. 
 
     
     
       3. The video signal processing device according to  claim 1 , wherein said video signal includes a series of n pixel data pieces which represent a luminance level of each pixel by first to k-th bits for each of the N frames, wherein n is an integer of 2 or more, and
 wherein said video signal dividing circuit is configured to divide said first to k-th bits of each of said n pixel data pieces for each bit in correspondence with said first to k-th division video signals, and generate first to k-th bit groups obtained by grouping bits of each of said n pixel data pieces corresponding to each other as said first to k-th division video signals. 
 
     
     
       4. The video signal processing device according to  claim 3 , wherein said video signal dividing circuit is configured to group said first to k-th bits of each of said n pixel data pieces for each same bit digit. 
     
     
       5. The video signal processing device according to  claim 3 , wherein said video signal dividing circuit is configured to change a correspondence relationship between said first to k-th bits and said first to k-th division video signals for each of said pixel data pieces when it divides said first to k-th bits of each of said n pixel data pieces for each bit in correspondence with said first to k-th division video signals. 
     
     
       6. A video freeze detecting circuit comprising:
 a video signal dividing circuit configured to receive a video signal including a series of N frames and a series of pixel data pieces for each of the N frames, and to divide said video signal into first to k-th division video signals for each of the N frames, wherein N is an integer of 2 or more, and k is an integer of 2 or more; 
 a video change detecting circuit configured to detect whether or not there is a difference in each of said first to k-th division video signals between adjacent frames of the N frames by comparing said first to k-th division video signals in one of the adjacent frames with said first to k-th division video signals in the other of the adjacent frames, respectively, and to generate first to k-th video change detection signals representing respective results of the detection; and 
 a freeze determination circuit configured to obtain an average number of a number of video change detection signals indicating that there is no difference among said first to k-th video change detection signals within a period of M frames of the N frames, and to output a freeze detection signal indicating that there is no change in a video based on said video signal when said average number is greater than a predetermined number, wherein M is an integer of 2 or more and M is N or less. 
 
     
     
       7. A method of detecting a video freeze comprising:
 a step of dividing a video signal including a series of N frames and a series of pixel data pieces for each of the N frames into first to k-th division video signals for each of the N frames, wherein N is an integer of 2 or more, and k is an integer of 2 or more; 
 a step of detecting whether or not there is a difference in each of said first to k-th division video signals between adjacent frames of the N frames by comparing said first to k-th division video signals in one of the adjacent frames with said first to k-th division video signals in the other of the adjacent frames, respectively, and of generating first to k-th video change detection signals representing respective results of the detection; and 
 a step of obtaining an average number of a number of video change detection signals indicating that there is no difference among said first to k-th video change detection signals within a period of M frames of the N frames, and of outputting a freeze detection signal indicating that there is no change in a video based on said video signal when said average number is greater than a predetermined number, wherein M is an integer of 2 or more and M is N or less.