Detailed failure notifications in memory sub-systems

Abstract

Disclosed is a system, and a method of using the system, that includes a memory component and a processing device. The processing device provides, to a host system, a failure notification that includes an indication of memory cell(s) of the memory device storing a data that was corrupted during a memory operation. The processing device then receives a replacement data from the host system. The replacement data is provided in response to the host system identifying a range of logical addresses corresponding to the corrupted data, based on geometric parameters of the memory device and the failure notification.

What is claimed is: 
     
       1. A system comprising:
 a memory device; and 
 a processing device, operatively coupled with the memory device, to perform operations comprising:
 providing a failure notification to a host system, wherein the failure notification comprises an indication of one or more memory cells of the memory device storing first data corrupted during a memory operation; and 
 receiving, from the host system, a second data to be stored in the memory device, in response to the host system identifying, based on geometric parameters of the memory device and the failure notification, a range of logical addresses corresponding to the indication of the one or more memory cells storing the corrupted first data. 
 
 
     
     
       2. The system of  claim 1 , wherein the corrupted first data comprises at least one of (i) a data attempted to be stored during the memory operation or (ii) a data stored prior to the memory operation. 
     
     
       3. The system of  claim 1 , wherein the indication of the one or more memory cells storing the corrupted first data comprises a physical address of the one or more memory cells storing the corrupted first data. 
     
     
       4. The system of  claim 1 , wherein the indication of the one or more memory cells storing the corrupted first data comprises a number of memory cells storing the corrupted first data. 
     
     
       5. The system of  claim 1 , wherein the second data comprises replacement data for the corrupted first data. 
     
     
       6. The system of  claim 5 , wherein the operations further comprise:
 executing a write operation to program the second data to the memory device. 
 
     
     
       7. The system of  claim 1 , wherein the geometric parameters of the memory device comprise at least one of:
 a number of memory cells that are to be programmed during a single write operation; 
 a number of memory cells to be used to program a logical memory page; 
 a logical address increment between a first physical partition of the memory device and a second physical partition of the memory device, wherein each of the first physical partition and the second physical partition comprise multiple memory cells; 
 information about a number of bits to be stored on a memory cell of the memory device; or 
 an order in which a plurality of memory cells of the memory device are to be programmed during a write operation. 
 
     
     
       8. A method comprising:
 providing, from a memory device, a failure notification to a host system, wherein the failure notification comprises an indication of one or more memory cells of the memory device storing first data corrupted during a memory operation; and 
 receiving, from the host system, a second data to be stored in the memory device, in response to the host system identifying, based on geometric parameters of the memory device and the failure notification, a range of logical addresses corresponding to the indication of the one or more memory cells storing the corrupted first data. 
 
     
     
       9. The method of  claim 8 , wherein the corrupted first data comprises at least one of (i) a data attempted to be stored during the memory operation or (ii) a data stored prior to the memory operation. 
     
     
       10. The method of  claim 8 , wherein the indication of the one or more memory cells storing the corrupted first data comprises a physical address of the one or more memory cells storing the corrupted first data. 
     
     
       11. The method of  claim 8 , wherein the indication of the one or more memory cells storing the corrupted first data comprises a number of memory cells storing the corrupted first data. 
     
     
       12. The method of  claim 8 , wherein the second data comprises replacement data for the corrupted first data. 
     
     
       13. The method of  claim 12 , further comprising:
 executing a write operation to program the second data to the memory device. 
 
     
     
       14. The method of  claim 8 , wherein the geometric parameters of the memory device comprise at least one of:
 a number of memory cells that are to be programmed during a single write operation; 
 a number of memory cells to be used to program a logical memory page; 
 a logical address increment between a first physical partition of the memory device and a second physical partition of the memory device, wherein each of the first physical partition and the second physical partition comprise multiple memory cells; 
 information about a number of bits to be stored on a memory cell of the memory device; or 
 an order in which a plurality of memory cells of the memory device are to be programmed during a write operation. 
 
     
     
       15. A non-transitory computer-readable medium storing instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
 providing, from a memory device, a failure notification to a host system, wherein the failure notification comprises an indication of one or more memory cells of the memory device storing first data corrupted during a memory operation; and 
 receiving, from the host system, a second data to be stored in the memory device, in response to the host system identifying, based on geometric parameters of the memory device and the failure notification, a range of logical addresses corresponding to the indication of the one or more memory cells storing the corrupted first data. 
 
     
     
       16. The non-transitory computer-readable medium of  claim 15 , wherein the corrupted first data comprises at least one of (i) a data attempted to be stored during the memory operation or (ii) a data stored prior to the memory operation. 
     
     
       17. The non-transitory computer-readable medium of  claim 15 , wherein the indication of the one or more memory cells storing the corrupted first data comprises at least some of:
 a physical address of the one or more memory cells storing the corrupted first data; or 
 a number of memory cells storing the corrupted first data. 
 
     
     
       18. The non-transitory computer-readable medium of  claim 15 , wherein the second data comprises replacement data for the corrupted first data. 
     
     
       19. The non-transitory computer-readable medium of  claim 18 , wherein the operations further comprise:
 executing a write operation to program the second data to the memory device. 
 
     
     
       20. The non-transitory computer-readable medium of  claim 15 , wherein the geometric parameters of the memory device comprise at least one of:
 a number of memory cells that are to be programmed during a single write operation; 
 a number of memory cells to be used to program a logical memory page; 
 a logical address increment between a first physical partition of the memory device and a second physical partition of the memory device, wherein each of the first physical partition and the second physical partition comprise multiple memory cells; 
 information about a number of bits to be stored on a memory cell of the memory device; or 
 an order in which a plurality of memory cells of the memory device are to be programmed during a write operation.