Multi-stage continuous time linear equalizer with reconfigurable inductor scheme

Abstract

A multi-stage continuous time linear equalizer (CTLE) with a reconfigurable inductor scheme is disclosed. The multi-stage CTLE comprises a first stage transformer-based inductive peaking and a second stage resistive load. The first stage transformer-based inductive peaking is configured to control high frequency peaking and set a peak frequency value to a desired value by using a coarse equalization mechanism. The stage resistive load configured to provide tuneable equalization and low frequency fine equalization by using a fine equalization mechanism.

We claim: 
     
       1. A multi-stage continuous time linear equalizer (CTLE) with a reconfigurable inductor scheme, the multi-stage CTLE comprising:
 a first stage transformer-based inductive-peaking configured to control high frequency peaking and set a peaking frequency to a desired value by performing a coarse equalization mechanism, wherein the first stage transformer-based inductive-peaking comprises:
 a first active transconductance (G m1 ) employed with current reuse topology to improve power consumption for a given amplification; 
 a passive transformer-based inductive load based on a transformer structure comprising:
 a primary coil composed of a center-tap differential inductor (L 1 ) configured to provide symmetric structure for signal amplification; 
 a common-mode voltage (V CM ) fed through a center tap; and 
 a secondary coil electromagnetically coupled to the primary coil, wherein the secondary coil comprises a resistor (R 2 ) placed in parallel to a secondary inductor (L 2 ); and 
 
 a load resistor (R L ) electrically connected in series with the first active transconductance (G m1 ) and the passive transformer-based inductive load; and 
 
 a second stage resistive load configured to provide tunable low frequency fine equalization by performing a fine equalization mechanism, wherein the second stage resistive load comprises:
 a second active transconductance (G m2 ) employed with current reuse topology, wherein the second active transconductance (G m2 ) comprises: 
 a source degeneration network of resistance and capacitance, and wherein the resistance and capacitance are implemented by using a metal-oxide semiconductor field-effect transistor (MOSFET) switch in triode and varactor diode respectively. 
 
 
     
     
       2. The multi-stage CTLE of  claim 1 , wherein the first stage transformer-based inductive-peaking and the second stage resistive load are calibrated by:
 performing the coarse equalization mechanism comprising: 
 i) calibrating an inductor value in the first stage transformer-based inductive-peaking by changing a value of the resistor (R 2 ) digitally via a digital to analog converter (DAC) to control the high frequency peaking; and 
 ii) controlling a value of the load resistor (R L ) to be approximately between a middle value of a predefined range to provide coarse equalization via controlling a low-frequency gain; and performing the fine equalization mechanism comprising: 
 iii) controlling the source degeneration network of the resistance and the capacitance in the second stage resistive load to provide fine equalization; and 
 iv) performing an equalization dynamic range check to ensure the multi-stage CTLE has sufficient dynamic range to counteract effects across Process, Voltage, and Temperature (PVT). 
 
     
     
       3. The multi-stage CTLE of  claim 2 , wherein the source degeneration network of the resistance and the capacitance is controlled by connecting and disconnecting a number of source degeneration slices, and wherein the number of source degeneration slices connected and disconnected are determined by monitoring a pulse response of an incoming signal and carrying at least one of the following two measurements: a) root mean square (RMS) sum of post and pre cursors and b) H 2  annulment, wherein H 2  is a value of the pulse response of the incoming signal after 2 unit intervals (UI). 
     
     
       4. The multi-stage CTLE of  claim 3 , wherein a fine equalization procedure is terminated when a target value of the at least one of the following two measurements is reached. 
     
     
       5. The multi-stage CTLE of  claim 3 , wherein upon calibration of the first stage transformer-based inductive-peaking and the second stage resistive load at start-up, data from the at least one of the following two measurements are accumulated in an n-bit accumulator, wherein n represents a real number. 
     
     
       6. The multi-stage CTLE of  claim 2 , wherein the equalization dynamic range check is performed by:
 determining whether a fine equalization code in the second stage resistive load is not centered, wherein centered is defined as within a pre-defined tolerance from all possible fine equalization codes; 
 changing the value of the load resistor (R L ) during the fine equalization mechanism based on the following conditions:
 a) respondent to the fine equalization code is equivalent to a lower code bound, increasing the value of the load resistor (R L ) by R L  Code=R L  Code+1 resulting in decrease in the amount of the coarse equalization in the first stage transformer-based inductive-peaking and thereby increasing the fine equalization required in the second stage resistive load; and 
 b) respondent to the fine equalization code is equivalent to an upper code bound, decreasing the value of the load resistor (R L ) by R L  Code=R L  Code−1 resulting in increase in the amount of coarse equalization in the first stage transformer-based inductive-peaking and thereby reducing the fine equalization required in the second stage resistive load; 
 
 wherein the steps ii)-iv) in  claim 2  are repeated until the fine equalization code is determined to be a centered code. 
 
     
     
       7. The multi-stage CTLE of  claim 1 , wherein the first active transconductance (G m1 ) is composed of a plurality of slices which are turned ON-OFF independently through digital configuration. 
     
     
       8. The multi-stage CTLE of  claim 1 , wherein the first active transconductance (G m1 ) and the second active transconductance (G m2 ) are employed with current reuse topology by using a stacked N-channel metal-oxide semiconductor (NMOS)/P-channel metal-oxide semiconductor (PMOS) amplifier. 
     
     
       9. The multi-stage CTLE of  claim 1 , wherein the multi-stage CTLE supports non-return-to-zero (NRZ) signaling and pulse amplitude modulation X-levels (PAM-X), wherein X represents a real number. 
     
     
       10. The multi-stage CTLE of  claim 1 , wherein the passive transformer-based inductive load employs a single structure for different frequencies. 
     
     
       11. The multi-stage CTLE of  claim 1 , wherein controlling the value of the resistor (R 2 ) of the secondary coil modifies an effective inductance at the primary coil and wherein the effective inductance is an imaginary part of an input impedance (Zin) by replacing s=σ+jω, wherein s is Laplace operator, σ is a real part of the Laplace operator and jω represents an imaginary part of the Laplace operator. 
     
     
       12. The multi-stage CTLE of  claim 1 , wherein the resistor (R 2 ) comprises of a passive resistor and a transistor-based resistor, wherein a gate of the transistor-based resistor is driven by a voltage generated by a digital to analog converter (DAC) controlled by configuration bits. 
     
     
       13. The multi-stage CTLE of  claim 1 , wherein a transfer function of the first stage transformer-based inductive-peaking is computed based on an output voltage (V o1 ) from the first stage transformer-based inductive-peaking, an input voltage (V in ) to the first stage transformer-based inductive-peaking, the first active transconductance (G m1 ), a load impedance value (Z load ), a transconductance of an N-channel metal-oxide semiconductor (NMOS) device (G mn ) in differential pair and a transconductance of a P-channel metal-oxide semiconductor (PMOS) device (g mp ) in differential pair respectively, the load resistor (R L ), the resistor (R 2 ), a load capacitance (C L ), the center-tap differential inductors (L 1 ), the secondary inductor (L 2 ), a coupling factor (k p ), and a Laplace transform symbol. 
     
     
       14. The multi-stage CTLE of  claim 1 , wherein the second stage resistive load further comprises a variant which has the source degeneration network of resistance and capacitance on at least one of N-channel metal-oxide semiconductor (NMOS) transistor and a P-channel metal-oxide semiconductor (PMOS) transistor section. 
     
     
       15. The multi-stage CTLE of  claim 1 , further comprising a complementary metal-oxide semiconductor (CMOS) topology enabling a high-Q load inductor to be realized as the load resistor (R L ) in series with the primary coil. 
     
     
       16. The multi-stage CTLE of  claim 15 , wherein the CMOS topology enables a variable output common-mode and the variable output common-mode is defined by a low-impedance variable V CM  source connected to the center tap of the primary coil. 
     
     
       17. A multi-stage continuous time linear equalizer (CTLE) method with a reconfigurable inductor scheme, the method comprising:
 calibrating a first stage transformer-based inductive-peaking by: 
 i) calibrating an inductor value in the first stage transformer-based inductive-peaking by changing a value of a resistor (R 2 ) digitally via a digital to analog convertor (DAC) to control high frequency peaking; and 
 ii) controlling a value of a load resistor (R L ) in between a middle value of a predefined range to provide coarse equalization via controlling a low-frequency gain; and 
 calibrating a second stage resistive load by: 
 iii) calibrating fine equalization by controlling a source degeneration network of resistance and capacitance by monitoring a pulse response of an incoming signal and carrying at least one of the following two measurements: a) root mean square (RMS) sum of post and pre cursors and b) H 2  annulment, wherein H 2  is a value of the pulse response of the incoming signal after 2 unit intervals (UI); and 
 iv) performing equalization dynamic range check to ensure the multi-stage CTLE has sufficient dynamic range to counteract effects across Process, Voltage, and Temperature (PVT) and to calibrate the second stage resistive load. 
 
     
     
       18. The multi-stage CTLE method of  claim 17 , wherein controlling the value of the load resistor (R L ) in between the middle value of the predefined range to provide the coarse equalization via controlling the low-frequency gain comprises:
 determining a number of source degeneration slices connected and disconnected by monitoring the pulse response of the incoming signal and carrying at least one of the following two measurements: a) the RMS sum of the post and pre cursors and b) the H 2  annulment, wherein; 
 determining whether a target value of the two measurements is reached; and 
 terminating a fine equalization procedure upon determining that the target value of the two measurements is reached. 
 
     
     
       19. The multi-stage CTLE method of  claim 18 , wherein a transfer function of the first stage transformer-based inductive-peaking is computed based on an output voltage (V o1 ) from the first stage transformer-based inductive-peaking, an input Voltage (V in ) to the first stage transformer-based inductive-peaking, a first active transconductance (G m1 ), a load impedance value (Z load ), a transconductance of an N-channel metal-oxide semiconductor (NMOS) device (G mn ) in differential pair and a transconductance of a P-channel metal-oxide semiconductor (PMOS) device (G mp ) in differential pair respectively, the load resistor (R L ), the resistor (R 2 ), a load capacitance (C L ), a center-tap differential inductors (L 1 ), a secondary inductor (L 2 ), a coupling factor (k p ), and a Laplace transform symbol. 
     
     
       20. The multi-stage CTLE method of  claim 17 , wherein performing the equalization dynamic range check to ensure the multi-stage CTLE has sufficient dynamic range to counteract effects across the Process, Voltage and Temperature (PVT) comprises:
 determining whether fine equalization code in the second stage resistive load is not centered and optimal; and 
 changing the value of the load resistor (R L ) using a fine equalization mechanism based on the following conditions: 
 a) if the fine equalization code is equivalent to a lower code bound, then increasing the value of the load resistor (R L ) by R L  Code=R L  Code+1 resulting in decrease in the amount of coarse equalization in the first stage transformer-based inductive-peaking and thereby increasing the fine equalization required in the second stage resistive load; and 
 b) if the fine equalization code is equivalent to an upper code bound, then decreasing the value of the load resistor (R L ) by R L  Code=R L  Code−1 resulting in increase in the amount of coarse equalization in the first stage transformer-based inductive-peaking and thereby reducing the fine equalization required in the second stage resistive load; and wherein the process steps ii)-iv) in  claim 17  are repeated until the fine equalization code is determined to be in a centered code. 
 
     
     
       21. The multi-stage CTLE method of  claim 17 , further comprising controlling the value of the resistor (R 2 ) of a secondary coil to modify effective inductance at a primary coil,
 wherein the effective inductance is an imaginary part of an input impedance (Zin) by replacing s=σ+jω, wherein Laplace operator, σ is a real part of the Laplace operator and jω represents an imaginary part of the Laplace operator.