Keep-through regions for handling end-of-line rules in routing

Abstract

A routing process applied to design integrated circuits uses keep-through regions. Keep-through regions specify areas which metal shapes may overlap but where metal shapes may not have line ends. The keep-through regions are generated based on end-of-line rules applicable to routing of the design. These keep-through regions are then used in determining the layout of interconnects for the design. The interconnects are composed of metal shapes, and the line ends of the metal shapes are located in accordance with the keep-through regions

The invention claimed is: 
     
       1. A method comprising:
 accessing a layout design of an integrated circuit, wherein the layout design has already been placed; and 
 applying, by a processor device, a routing process to the layout design, the routing process comprising:
 generating keep-through regions for the layout design based on end-of-line rules applicable to routing of interconnects for the layout design, wherein the keep-through regions specify areas in the layout design where metal shapes laid out as part of the routing process are allowed to overlap with the keep-through region, but line ends of the metal shapes are not allowed to be located within the keep-through region; and 
 determining a layout of interconnects for the layout design, the layout of interconnects comprising metal shapes having line ends in accordance with the keep-through regions; wherein determining the layout of interconnects comprises locating a line end of at least one of the metal shapes within one of the keep-through regions, and then extending the metal shape so that the line end is no longer located within the keep-through regions; wherein determining the layout of interconnects is performed progressively for a plurality of interconnects, and generating the keep-through regions comprises generating the keep-through regions for completed interconnects. 
 
 
     
     
       2. The method of  claim 1  wherein at least some of the keep-through regions are generated based on rules for line end spacing for cut-metal shapes. 
     
     
       3. The method of  claim 1  wherein at least some of the keep-through regions are generated based on rules for line end spacing for soft requirements of cut-metal shapes. 
     
     
       4. The method of  claim 1  wherein generating the keep-through regions further comprises generating the keep-through regions for trial metal shapes of interconnects currently being routed. 
     
     
       5. The method of  claim 1  wherein the interconnects are laid out in tracks; and determining the layout of interconnects comprises determining maximum available metal spaces on the tracks in accordance with the keep-through regions, and then determining the layout of interconnects within the maximum available metal spaces. 
     
     
       6. The method of  claim 5  wherein the maximum available metal spaces are determined by first applying keep-out regions and then applying keep-through regions, wherein the keep-out regions specify areas in the layout design which the metal shapes are not allowed to overlap with the keep-out region. 
     
     
       7. The method of  claim 6  further comprising converting keep-through regions located at ends of maximum available metal spaces to keep-out regions. 
     
     
       8. The method of  claim 1  wherein determining the layout of interconnects further comprises
 costing the extensions of metal shapes in determining the layout. 
 
     
     
       9. A system comprising:
 a memory storing instructions; and 
 a processor device, coupled with the memory and to execute the instructions, the instructions when executed cause the processor device to apply a routing process to a layout design of an integrated circuit that has already been placed, the routing process comprising:
 generating keep-through regions for the layout design based on end-of-line rules applicable to routing of interconnects for the layout design, wherein the interconnects comprise shapes, the keep-through regions specify areas in the layout design where the shapes are allowed to overlap with the keep-through region, but the line ends of the shapes are not allowed to be located within the keep-through region; and 
 determining a layout of the interconnects for the layout design, the layout of interconnects comprising shapes having line ends in accordance with the keep-through wherein determining the layout of interconnects comprises locating a line end of at least one of the shapes within one of the keep-through regions, and then extending the shape so that the line end is no longer located within the keep-through region; and wherein determining the layout of interconnects is performed progressively for a plurality of interconnects, and generating the keep-through regions comprises generating the keep-through regions for completed interconnects. 
 
 
     
     
       10. The system of  claim 9  wherein determining the layout of interconnects comprises locating a line end of at least one of the shapes within a keep-through region and then truncating or extending the metal shape so that the line end is no longer located within the keep-through region. 
     
     
       11. The system of  claim 9  wherein the interconnects are laid out in tracks; and at least some keep-through regions generated for the shapes on one track also apply to shapes on adjacent tracks. 
     
     
       12. The system of  claim 9  wherein at least some keep-through regions are directional, wherein shapes entering the keep-through region from one side are not allowed to have line ends in the keep-through region but shapes entering the keep-through region from an opposite side are allowed to have line ends in the keep-through region. 
     
     
       13. The system of  claim 9  wherein determining the layout of interconnects comprises merging keep-through regions, and then determining the layout of interconnects in accordance with the merged keep-through regions. 
     
     
       14. The system of  claim 9  wherein the layout design for the integrated circuit is based on a 20 nm or more advanced process technology node. 
     
     
       15. A non-transitory computer readable medium comprising stored instructions, which when executed by a processor device, cause the processor device to apply a routing process to progressively determine interconnects for a layout design of an integrated circuit that has already been placed, the routing process comprising, for a current set of routes under consideration:
 generating keep-through regions for the layout design based on end-of-line rules applicable to previously completed routes, wherein the keep-through regions specify areas in the layout design where metal shapes laid out as part of the routing process are allowed to overlap with the keep-through region, but line ends of the metal shapes are not allowed to be located within the keep-through region; and 
 determining a layout of the current set of routes, the determined layout of the current set of routes comprising metal shapes having line ends in accordance with the keep-through wherein determining the layout of the current set of routes comprises locating a line end of at least one of the metal shapes within one of the keep-through regions, and then extending the metal shape so that the line end is no longer located within the keep-through region; and the routing process is performed progressively for a plurality of routes, and generating the keep-through regions comprises generating the keep-through regions for previously completed routes. 
 
     
     
       16. The non-transitory computer readable medium of  claim 15  wherein the routing process further comprises:
 identifying line ends of metal shapes from previously completed routes, based on a width and length of convex local features of the metal shapes. 
 
     
     
       17. The non-transitory computer readable medium of  claim 15  wherein determining the layout of interconnects further comprises:
 costing the extensions of metal shapes in determining the layout.