Searchable array circuits with load-matched signals for reduced hit signal timing margins and related methods

Abstract

A CAM array of compare memory cell circuits includes a decode column corresponding to each set, and each set includes at least one row of the compare memory cell circuits. Each decode column receives a set clock signal addressing the corresponding set and generates a set match signal in each row of the corresponding set. A column compare circuit generates compare data indicating a bit of a compare tag. A row match circuit generates, for each row, in response to the set match signal, a row match signal indicating the compare tag matches the binary tag stored in the row. Circuits and loads in a decode column employed to generate the set clock signal correspond to circuits generating the row match signal in each column of the CAM array to reduce a timing margin of the match indication and decrease the access time for the CAM array.

What is claimed is: 
     
       1. An array of compare memory cell circuits comprising:
 at least one set, each set comprising at least one row of a plurality of rows of compare memory cell circuits, each row of the plurality of rows configured to store a binary tag; 
 a plurality of columns of the compare memory cell circuits, each column of the plurality of columns comprising a compare memory cell circuit in each row of the plurality of rows; 
 at least one decode column, each of the at least one decode column corresponding to a set of the at least one set, the at least one decode column configured to:
 receive a set clock signal for the corresponding set; and 
 generate a set match signal on a set match line in each row of the corresponding set; and 
 
 a dynamic comparator circuit comprising:
 a set clock circuit configured to generate, to each of the at least one decode column, the set clock signal for addressing the corresponding set; 
 a column compare circuit configured to generate, for each column of the plurality of columns, a compare true data indicating a compare true bit of a compare tag; 
 a row match circuit configured to generate, for each row of the plurality of rows, in response to the set match signal generated in the row, a row match signal indicating that the compare tag matches the binary tag stored in the row, 
 
 wherein: 
 each decode column of the at least one decode column comprises a pull-down circuit in each row of the plurality of rows of compare memory cell circuits, each pull-down circuit coupled to the set match line in the corresponding row; and 
 in a decode column corresponding to a set of the at least one set:
 each pull-down circuit corresponding to a row in the set is configured to activate the set match line in the row in response to receiving the set clock signal for the corresponding set; and 
 each pull-down circuit corresponding to a row in another set of the at least one set is configured to not activate the set match line in the row. 
 
 
     
     
       2. The array of compare memory cell circuits of  claim 1 , each row of the plurality of rows further comprising a row match line, wherein the row match circuit is further configured to generate the row match signal for the row in response to the row match line indicating the compare tag matches the binary tag stored in the row. 
     
     
       3. The array of compare memory cell circuits of  claim 2 , wherein each compare memory cell circuit is configured to store a stored true data corresponding to a compare true bit of the binary tag and a stored complement data complementary to the stored true data. 
     
     
       4. The array of compare memory cell circuits of  claim 3 , each compare memory cell circuit further comprising a true compare circuit coupled to:
 the row match line of the row comprising the compare memory cell circuit; and 
 a true compare bit line configured to receive the compare true data for the column comprising the compare memory cell circuit; 
 wherein the true compare circuit is configured to couple the row match line to a first voltage to indicate that the compare true data received on the true compare bit line does not match the stored true data stored in the compare memory cell circuit. 
 
     
     
       5. The array of compare memory cell circuits of  claim 4 , wherein:
 the column compare circuit is further configured to generate, for each column of the plurality of columns, a compare complement data complementary to the compare true data of the binary tag and indicating a compare complement bit of the compare tag; and 
 each compare memory cell circuit further comprises a complement compare circuit configured to couple the row match line of the row comprising the memory cell circuit to the first voltage to indicate that the compare complement data for the column comprising the compare memory cell circuit does not match the stored complement data stored in the compare memory cell circuit. 
 
     
     
       6. The array of compare memory cell circuits of  claim 5 , the complement compare circuit further comprising a third transistor controlled by the stored complement data stored in the compare memory cell circuit and a fourth transistor controlled by the compare true data for the column comprising the compare memory cell circuit. 
     
     
       7. The array of compare memory cell circuits of  claim 4 , the true compare circuit further comprising a first transistor controlled by the stored true data stored in the compare memory cell circuit and a second transistor controlled by the compare complement data for the column comprising the compare memory cell circuit. 
     
     
       8. The array of compare memory cell circuits of  claim 3 , wherein each of the compare memory cell circuits comprise a static random-access memory (SRAM) cell circuit. 
     
     
       9. The array of compare memory cell circuits of  claim 1 , the set clock circuit is further configured to generate, to each of the at least one decode column, the set clock signal in response to a clock signal and a set address signal corresponding to the set. 
     
     
       10. The array of compare memory cell circuits of  claim 1 , the column compare circuit is further configured to generate, for each column of the plurality of columns, the compare true data based on the compare true bit of the binary tag in response to the clock signal. 
     
     
       11. The array of compare memory cell circuits of  claim 1 , wherein:
 each decode column is configured to receive the set clock signal for the corresponding set generated by the set clock circuit; and 
 each pull-down circuit comprises a first transistor controlled by the set clock signal and a second transistor coupled to a fixed voltage source. 
 
     
     
       12. The array of compare memory cell circuits of  claim 11 , wherein:
 in each row in the corresponding set, the voltage source comprises a supply voltage VDD; and 
 in each row not in the corresponding set, the voltage source comprises a ground voltage Vss. 
 
     
     
       13. The array of compare memory cell circuits of  claim 11 , wherein:
 each decode column further comprises, in each row, a non-compare memory cell circuit coupled to a read bit line, the non-compare memory cell circuit comprising: 
 a memory cell circuit; and 
 a read transistor circuit configured to read a stored data stored in the non-compare memory cell circuit in response to activation of a read word signal. 
 
     
     
       14. An integrated circuit comprising an array of compare memory cell circuits, the array of compare memory cell circuits comprising:
 at least one set, each set comprising at least one row of a plurality of rows of compare memory cell circuits, each row of the plurality of rows configured to store a binary tag; 
 a plurality of columns of the compare memory cell circuits, each column of the plurality of columns comprising a compare memory cell circuit in each row of the plurality of rows; 
 at least one decode column, each of the at least one decode column corresponding to a set of the at least one set, the at least one decode column configured to:
 receive a set clock signal for the corresponding set; and 
 generate a set match signal on a set match line in each row of the corresponding set; and 
 
 a dynamic comparator circuit comprising:
 a set clock circuit configured to generate, to each of the at least one decode column, the set clock signal for addressing the corresponding set; 
 a column compare circuit configured to generate, for each column of the plurality of columns, a compare true data indicating a compare true bit of a compare tag; and 
 a row match circuit configured to generate, for each row of the plurality of rows, in response to the set match signal generated in the row, a row match signal indicating that the compare tag matches the binary tag stored in the row, 
 
 wherein: 
 each decode column of the at least one decode column comprises a pull-down circuit in each row of the plurality of rows of compare memory cell circuits, each pull-down circuit coupled to the set match line in the corresponding row; and 
 in a decode column corresponding to a set of the at least one set:
 each pull-down circuit corresponding to a row in the set is configured to activate the set match line in the row in response to receiving the set clock signal for the corresponding set; and 
 each pull-down circuit corresponding to a row in another set of the at least one set is configured to not activate the set match line in the row. 
 
 
     
     
       15. The integrated circuit of  claim 14 , each row of the plurality of rows further comprising a row match line, wherein the row match circuit is further configured to generate the row match signal for the row in response to the row match line indicating the compare tag matches the binary tag stored in the row. 
     
     
       16. The integrated circuit of  claim 15 , wherein each compare memory cell circuit is configured to store a stored true data corresponding to a compare true bit of the binary tag and a stored complement data complementary to the stored true data. 
     
     
       17. The integrated circuit of  claim 16 , each compare memory cell circuit further comprising a true compare circuit coupled to:
 the row match line of the row comprising the compare memory cell circuit; and 
 a true compare bit line configured to receive the compare true data for the column comprising the compare memory cell circuit; 
 wherein the true compare circuit is configured to couple the row match line to a first voltage to indicate that the compare true data received on the true compare bit line does not match the stored true data stored in the compare memory cell circuit. 
 
     
     
       18. The integrated circuit of  claim 17 , wherein:
 the column compare circuit is further configured to generate, for each column of the plurality of columns, a compare complement data complementary to the compare true data of the binary tag and indicating a compare complement bit of the compare tag; and 
 each compare memory cell circuit further comprises a complement compare circuit configured to couple the row match line of the row comprising the memory cell circuit to the first voltage to indicate that the compare complement data for the column comprising the compare memory cell circuit does not match the stored complement data stored in the compare memory cell circuit. 
 
     
     
       19. The integrated circuit of  claim 17 , the true compare circuit further comprising a first transistor controlled by the stored true data stored in the compare memory cell circuit and a second transistor controlled by the compare complement data for the column comprising the compare memory cell circuit. 
     
     
       20. The integrated circuit of  claim 19 , the complement compare circuit further comprising a third transistor controlled by the stored complement data stored in the compare memory cell circuit and a fourth transistor controlled by the compare true data for the column comprising the compare memory cell circuit. 
     
     
       21. An array of compare memory cell circuits comprising:
 at least one set, each set comprising at least one row of a plurality of rows of compare memory cell circuits, each row of the plurality of rows configured to store a binary tag; 
 a plurality of columns of the compare memory cell circuits, each column of the plurality of columns comprising a compare memory cell circuit in each row of the plurality of rows; 
 at least one decode column, each of the at least one decode column corresponding to a set of the at least one set, the at least one decode column configured to:
 receive a set clock signal for the corresponding set; and 
 generate a set match signal on a set match line in each row of the corresponding set; and 
 
 a dynamic comparator circuit comprising:
 a set clock circuit configured to generate, to each of the at least one decode column, the set clock signal for addressing the corresponding set; 
 a column compare circuit configured to generate, for each column of the plurality of columns, a compare true data indicating a compare true bit of a compare tag; 
 a row match circuit configured to generate, for each row of the plurality of rows, in response to the set match signal generated in the row, a row match signal indicating that the compare tag matches the binary tag stored in the row, 
 
 wherein, in each of the at least one decode columns:
 the set clock signal is coupled to a load in each row of each set of the array; and 
 the load in each row of the set corresponding to the decode column comprises a circuit controlling the set match signal. 
 
 
     
     
       22. The array of compare memory cell circuits of  claim 21 , each row of the plurality of rows further comprising a row match line, wherein the row match circuit is further configured to generate the row match signal for the row in response to the row match line indicating the compare tag matches the binary tag stored in the row. 
     
     
       23. The array of compare memory cell circuits of  claim 22 , wherein each compare memory cell circuit is configured to store a stored true data corresponding to a compare true bit of the binary tag and a stored complement data complementary to the stored true data. 
     
     
       24. The array of compare memory cell circuits of  claim 23 , each compare memory cell circuit further comprising a true compare circuit coupled to:
 the row match line of the row comprising the compare memory cell circuit; and 
 a true compare bit line configured to receive the compare true data for the column comprising the compare memory cell circuit; 
 wherein the true compare circuit is configured to couple the row match line to a first voltage to indicate that the compare true data received on the true compare bit line does not match the stored true data stored in the compare memory cell circuit. 
 
     
     
       25. The array of compare memory cell circuits of  claim 24 , wherein:
 the column compare circuit is further configured to generate, for each column of the plurality of columns, a compare complement data complementary to the compare true data of the binary tag and indicating a compare complement bit of the compare tag; and 
 each compare memory cell circuit further comprises a complement compare circuit configured to couple the row match line of the row comprising the memory cell circuit to the first voltage to indicate that the compare complement data for the column comprising the compare memory cell circuit does not match the stored complement data stored in the compare memory cell circuit. 
 
     
     
       26. The array of compare memory cell circuits of  claim 25 , the complement compare circuit further comprising a third transistor controlled by the stored complement data stored in the compare memory cell circuit and a fourth transistor controlled by the compare true data for the column comprising the compare memory cell circuit. 
     
     
       27. The array of compare memory cell circuits of  claim 24 , the true compare circuit further comprising a first transistor controlled by the stored true data stored in the compare memory cell circuit and a second transistor controlled by the compare complement data for the column comprising the compare memory cell circuit. 
     
     
       28. The array of compare memory cell circuits of  claim 21 , the set clock circuit is further configured to generate, to each of the at least one decode column, the set clock signal in response to a clock signal and a set address signal corresponding to the set. 
     
     
       29. The array of compare memory cell circuits of  claim 21 , the column compare circuit is further configured to generate, for each column of the plurality of columns, the compare true data based on the compare true bit of the binary tag in response to the clock signal. 
     
     
       30. An array of compare memory cell circuits comprising:
 at least one set, each set comprising at least one row of a plurality of rows of compare memory cell circuits, each row of the plurality of rows configured to store a binary tag; 
 a plurality of columns of the compare memory cell circuits, each column of the plurality of columns comprising a compare memory cell circuit in each row of the plurality of rows; 
 at least one decode column, each of the at least one decode column corresponding to a set of the at least one set, the at least one decode column configured to:
 receive a set clock signal for the corresponding set; and 
 generate a set match signal on a set match line in each row of the corresponding set; and 
 
 a dynamic comparator circuit comprising:
 a set clock circuit configured to generate, to each of the at least one decode column, the set clock signal for addressing the corresponding set; 
 a column compare circuit configured to generate, for each column of the plurality of columns, a compare true data indicating a compare true bit of a compare tag; and 
 a row match circuit comprising a delay circuit configured to generated a delayed set match signal based on the set match signal generated in the row, wherein the row match circuit is configured to generate, for each row of the plurality of rows, in response to the delayed set match signal, a row match signal indicating that the compare tag matches the binary tag stored in the row. 
 
 
     
     
       31. The array of compare memory cell circuits of  claim 30 , each row of the plurality of rows further comprising a row match line, wherein the row match circuit is further configured to generate the row match signal for the row in response to the row match line indicating the compare tag matches the binary tag stored in the row. 
     
     
       32. The array of compare memory cell circuits of  claim 31 , wherein each compare memory cell circuit is configured to store a stored true data corresponding to a compare true bit of the binary tag and a stored complement data complementary to the stored true data. 
     
     
       33. The array of compare memory cell circuits of  claim 32 , each compare memory cell circuit further comprising a true compare circuit coupled to:
 the row match line of the row comprising the compare memory cell circuit; and 
 a true compare bit line configured to receive the compare true data for the column comprising the compare memory cell circuit; 
 wherein the true compare circuit is configured to couple the row match line to a first voltage to indicate that the compare true data received on the true compare bit line does not match the stored true data stored in the compare memory cell circuit. 
 
     
     
       34. The array of compare memory cell circuits of  claim 33 , wherein:
 the column compare circuit is further configured to generate, for each column of the plurality of columns, a compare complement data complementary to the compare true data of the binary tag and indicating a compare complement bit of the compare tag; and 
 each compare memory cell circuit further comprises a complement compare circuit configured to couple the row match line of the row comprising the memory cell circuit to the first voltage to indicate that the compare complement data for the column comprising the compare memory cell circuit does not match the stored complement data stored in the compare memory cell circuit. 
 
     
     
       35. The array of compare memory cell circuits of  claim 34 , the complement compare circuit further comprising a third transistor controlled by the stored complement data stored in the compare memory cell circuit and a fourth transistor controlled by the compare true data for the column comprising the compare memory cell circuit. 
     
     
       36. The array of compare memory cell circuits of  claim 33 , the true compare circuit further comprising a first transistor controlled by the stored true data stored in the compare memory cell circuit and a second transistor controlled by the compare complement data for the column comprising the compare memory cell circuit. 
     
     
       37. The array of compare memory cell circuits of  claim 30 , the set clock circuit is further configured to generate, to each of the at least one decode column, the set clock signal in response to a clock signal and a set address signal corresponding to the set. 
     
     
       38. The array of compare memory cell circuits of  claim 30 , the column compare circuit is further configured to generate, for each column of the plurality of columns, the compare true data based on the compare true bit of the binary tag in response to the clock signal.