Compiler-optimized context switching with compiler-inserted data table for in-use register identification at a preferred preemption point

Abstract

Compiler-optimized context switching may include receiving an instruction indicating a preferred preemption point comprising an instruction address; storing the preferred preemption point in a data structure; determining, based on the data structure, that the preferred preemption point has been reached by a first thread; determining that preemption of the first thread for a second thread has been requested; and performing a context switch to the second thread.

What is claimed is: 
     
       1. A method of compiler-optimized context switching, the method comprising:
 receiving processor-executable instructions indicating a preferred preemption point comprising an instruction address, wherein a compiler inserts, into the processor-executable instructions, a data table indicating which context registers of a plurality of context registers are in use at the preferred preemption point, and wherein the processor-executable instructions further comprise additional instructions to update the data table during the execution of the processor-executable instructions; 
 storing the preferred preemption point in a data structure; 
 determining, based on the data structure, that the preferred preemption point has been reached by a first thread; 
 determining that preemption of the first thread for a second thread has been requested; and 
 performing a context switch to the second thread, wherein performing the context switch to the second thread comprises overwriting each of the plurality of context registers prior to loading one or more context registers, of the plurality of context registers, used by the second thread. 
 
     
     
       2. The method of  claim 1 , wherein the processor-executable instructions indicating the preferred preemption point comprise a first operand representing the instruction address of the preferred preemption point and a second operand representing an N-bit hash code index specifying which of a plurality of preferred preemption points to overwrite within the data structure. 
     
     
       3. The method of  claim 2 , wherein performing the context switch to the second thread comprises:
 determining one or more context registers, of the plurality of context registers, used by the first thread, including referencing the data table; and 
 saving values stored in the determined one or more context registers prior to overwriting each of the plurality of context registers. 
 
     
     
       4. The method of  claim 3 , wherein performing the context switch to the second thread comprises:
 causing an exception handler to interrupt execution of the first thread; and 
 saving values held in context registers within the exception handler. 
 
     
     
       5. The method of  claim 3 , wherein determining the one or more context registers, of the plurality of context registers, used by the first thread comprises:
 obtaining a value of a hash code that identifies which particular preemption point of the plurality of preferred preemption points was encountered by consulting a register; and 
 consulting the data table which describes which context registers are in use at the particular preemption point. 
 
     
     
       6. The method of  claim 3 , wherein determining the one or more context registers, of the plurality of context registers, used by the first thread comprises:
 obtaining an address of an instruction that was recognized as a second preferred preemption point by consulting a register; and 
 using the recognized address of the instruction as a hash code to consult the data table which describes which context registers are in use at the second preferred preemption point. 
 
     
     
       7. The method of  claim 1 , wherein the received processor-executable instructions indicate a plurality of preferred preemption points, each comprising an instruction address, wherein the data table inserted into the processor-executable instructions indicates which context registers of the plurality of context registers are in use at each of the plurality of preferred preemption points. 
     
     
       8. An apparatus for compiler-optimized context switching, the apparatus comprising a processor, wherein the processor of the apparatus is configured to perform steps comprising:
 receiving processor-executable instructions indicating a preferred preemption point comprising an instruction address, wherein a compiler inserts, into the processor-executable instructions, a data table indicating which context registers of a plurality of context registers are in use at the preferred preemption point, and wherein the processor-executable instructions further comprise additional instructions to update the data table during the execution of the processor-executable instructions; 
 storing the preferred preemption point in a data structure; 
 determining based on the data structure, that the preferred preemption point has been reached by a first thread; 
 determining that preemption of the first thread for a second thread has been requested; and 
 performing a context switch to the second thread, wherein performing the context switch to the second thread comprises overwriting each of the plurality of context registers prior to loading one or more context registers, of the plurality of context registers, used by the second thread. 
 
     
     
       9. The apparatus of  claim 8 , wherein the processor-executable instructions indicating the preferred preemption point comprise a first operand representing the instruction address of the preferred preemption point and a second operand representing an N-bit hash code index specifying which of a plurality of preferred preemption points to overwrite within the data structure. 
     
     
       10. The apparatus of  claim 9 , wherein performing, by the processor, the context switch to the second thread comprises:
 determining one or more context registers, of the plurality of context registers, used by the first thread; and 
 saving values stored in the determined one or more context registers prior to overwriting each of the plurality of context registers. 
 
     
     
       11. The apparatus of  claim 10 , wherein performing, by the processor, the context switch to the second thread comprises:
 causing an exception handler to interrupt execution of the first thread; and 
 saving values held in context registers within the exception handler. 
 
     
     
       12. The apparatus of  claim 10 , wherein determining the one or more context registers, of the plurality of context registers, used by the first thread comprises:
 obtaining a value of a hash code that identifies which particular preemption point of the plurality of preferred preemption points was encountered by consulting a register; and 
 consulting the data table which describes which context registers are in use at the particular preemption point. 
 
     
     
       13. The apparatus of  claim 10 , wherein determining the one or more context registers, of the plurality of context registers, used by the first thread comprises:
 obtaining an address of an instruction that was recognized as a second preferred preemption point by consulting a register; and 
 using the recognized address of the instruction as a hash code to consult the data table which describes which context registers are in use at the second preferred preemption point. 
 
     
     
       14. The apparatus of  claim 8 , wherein the received processor-executable instructions indicate a plurality of preferred preemption points, each comprising an instruction address, wherein the data table inserted into the processor-executable instructions indicates which context registers of the plurality of context registers are in use at each of the plurality of preferred preemption points. 
     
     
       15. A computer program product for compiler-optimized context switching, the computer program product disposed upon a non-transitory computer readable medium, the computer program product comprising computer program instructions that, when executed, cause a computer to carry out the steps of:
 receiving processor-executable instructions indicating a preferred preemption point comprising an instruction address, wherein a compiler inserts, into the processor-executable instructions, a data table indicating which context registers of a plurality of context registers are in use at the preferred preemption point, and wherein the processor-executable instructions further comprise additional instructions to update the data table during the execution of the processor-executable instructions; 
 storing the preferred preemption point in a data structure; 
 determining, based on the data structure, that the preferred preemption point has been reached by a first thread; 
 determining that preemption of the first thread for a second thread has been requested; and 
 performing a context switch to the second thread, wherein performing the context switch to the second thread comprises overwriting each of the plurality of context registers prior to loading one or more context registers, of the plurality of context registers, used by the second thread. 
 
     
     
       16. The computer program product of  claim 15 , wherein the processor-executable instructions indicating the preferred preemption point comprise a first operand representing the instruction address of the preferred preemption point and a second operand representing an N-bit hash code index specifying which of a plurality of preferred preemption points to overwrite within the data structure. 
     
     
       17. The computer program product of  claim 16 , wherein performing the context switch to the second thread comprises:
 determining one or more context registers, of the plurality of context registers, used by the first thread; and 
 saving values stored in the determined one or more context registers prior to overwriting each of the plurality of context registers. 
 
     
     
       18. The computer program product of  claim 17 , wherein performing the context switch to the second thread comprises:
 causing an exception handler to interrupt execution of the first thread; and 
 saving values held in context registers within the exception handler. 
 
     
     
       19. The computer program product of  claim 17 , wherein determining the one or more context registers, of the plurality of context registers, used by the first thread comprises:
 obtaining a value of a hash code that identifies which particular preemption point of the plurality of preferred preemption points was encountered by consulting a register; and 
 consulting the data table which describes which context registers are in use at the particular preemption point. 
 
     
     
       20. The computer program product of  claim 15 , wherein the received processor-executable instructions indicate a plurality of preferred preemption points, each comprising an instruction address, wherein the data table inserted into the processor-executable instructions indicates which context registers of the plurality of context registers are in use at each of the plurality of preferred preemption points.