System and method of testing a semiconductor device

Abstract

A system for testing a semiconductor may include a transfer chamber, at least one loadlock chamber and at least one test chamber. The transfer chamber may include a plurality of sidewalls. The loadlock chamber may be arranged on a first sidewall of the sidewalls of the transfer chamber. The loadlock chamber may include a carrier configured to receive a plurality of wafers. The test chamber may be arranged on a second sidewall of the sidewalls of the transfer chamber. When the transfer chamber is connected to the loadlock chamber, a pressure of the transfer chamber may be changed into a pressure of the loadlock chamber. When the transfer chamber is connected to the test chamber, the pressure of the transfer chamber may be changed into a pressure of the test chamber.

What is claimed is: 
     
       1. A semiconductor test system comprising:
 a transfer chamber; 
 at least one loadlock chamber arranged around the transfer chamber to receive a plurality of wafers; and 
 at least one test chamber arranged around the transfer chamber, the test chamber having a cryogenic temperature and a high vacuum, 
 wherein the test chamber has a first internal pressure and the loadlock chamber has a second internal pressure higher than the first internal pressure, and 
 wherein an internal pressure of the transfer chamber is changed to be substantially the same as the first internal pressure for transferring the wafer between the transfer chamber and the test chamber, and the internal pressure of the transfer chamber is changed to be substantially the same as the second internal pressure for transferring the wafer between the transfer chamber and the loadlock chamber. 
 
     
     
       2. The semiconductor test system of  claim 1 , wherein the transfer chamber comprises a plurality of sidewalls, the loadlock chamber is positioned at one of the sidewalls, and the test chamber is positioned at the other of the sidewalls. 
     
     
       3. The semiconductor test system of  claim 1 , wherein the transfer chamber comprises a pump configured to control the internal pressure of the transfer chamber. 
     
     
       4. The semiconductor test system of  claim 1 , wherein the test chamber comprises:
 a cooling tank configured to supply a cooling source to the test chamber; 
 a pump configured to provide the test chamber with the high vacuum; and 
 a flow sensor installed in the cooling tank to periodically sense an amount of the cooling source in the cooling tank. 
 
     
     
       5. The semiconductor test system of  claim 4 , wherein the flow sensor senses the amount of the cooling source in the cooling tank before transferring the wafer to the test chamber. 
     
     
       6. The semiconductor test system of  claim 1 , wherein the test chamber has a temperature of −50° C. to −196° C. and a pressure of 10 −5  torr to 10 −7  torr. 
     
     
       7. The semiconductor test system of  claim 6 , wherein the test chamber comprises a prober configured to perform a probe test on the wafer transferred to the test chamber. 
     
     
       8. A semiconductor test system comprising:
 a transfer chamber including a transfer unit; 
 a plurality of loadlock chambers arranged around the transfer chamber in a cluster shape; 
 a plurality of test chambers arranged around the transfer chamber in the cluster shape; and 
 a control module configured to control operations of the transfer chamber, the loadlock chambers and the test chambers, 
 wherein the test chambers are configured to perform a probe test under a cryogenic environment, 
 wherein a wafer in any one of the loadlock chambers is transferred to the test chamber through the transfer chamber by the transfer unit, and the tested wafer in the test chamber is transferred to the loadlock chamber through the transfer chamber by the transfer unit, 
 wherein the test chamber has a first internal pressure and the loadlock chamber has a second internal pressure higher than the first internal pressure, and 
 wherein the control module changes an internal pressure of the transfer chamber to be substantially the same as the first internal pressure for transferring the wafer between the transfer chamber and the test chamber, and the control module changes the internal pressure of the transfer chamber to be substantially the same as the second internal pressure for transferring the wafer between the transfer chamber and the loadlock chamber. 
 
     
     
       9. The semiconductor test system of  claim 8 , wherein the test chamber continuously has the cryogenic environment, and the test chambers are configured to sequentially perform the probe test. 
     
     
       10. The semiconductor test system of  claim 8 , wherein each of the test chambers comprises a cooling tank and a pump configured to provide the test chambers with the cryogenic environment. 
     
     
       11. The semiconductor test system of  claim 10 , wherein each of the test chambers further comprises a flow sensor configured to periodically sense an amount of a cooling source in the cooling tank. 
     
     
       12. A method of driving a semiconductor test system, the semiconductor test system including a transfer chamber including a transfer unit, and a plurality of loadlock chambers and a plurality of test chambers arranged around the transfer chamber in a cluster shape, the method comprising:
 providing the test chambers with a cryogenic environment having a cryogenic temperature and a high vacuum; 
 transferring a first wafer in any one of the loadlock chambers to the transfer chamber; 
 providing the transfer chamber with the first wafer with a high vacuum substantially the same as the high vacuum of the test chambers; 
 transferring the first wafer in the transfer chamber to a first test chamber among the test chambers in which a cryogenic probe test has not been performed; and 
 performing the cryogenic probe test on the first wafer. 
 
     
     
       13. The method of  claim 12 , further comprising during performing the cryogenic probe test on the first wafer:
 changing an internal pressure of the transfer chamber into an atmospheric pressure; 
 transferring a second wafer in any one of the loadlock chambers to the transfer chamber; 
 providing the transfer chamber with the second wafer with the high vacuum; 
 transferring the second wafer in the transfer chamber to a second test chamber among the test chamber in which the cryogenic probe test has not been performed; and 
 performing the cryogenic probe test on the second wafer. 
 
     
     
       14. The method of  claim 12 , further comprising checking an internal pressure and an internal temperature of the test chamber before transferring the first wafer to the first test chamber,
 wherein the first wafer is transferred to the first test chamber when the internal pressure and the internal temperature of the test chamber correspond to the cryogenic environment. 
 
     
     
       15. The method of  claim 12 , further comprising before transferring the first wafer to the first test chamber:
 sensing an amount of a cooling source in the first test chamber; 
 providing the first test chamber with a room temperature and an atmospheric pressure when a sensed amount of the cooling source in the first test chamber is no more than a critical amount; and 
 filling the first test chamber with the cooling source.