Microelectronic devices with through-substrate interconnects and associated methods of manufacturing

Abstract

Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.

We claim: 
     
       1. A method for fabricating a semiconductor device, comprising:
 forming a first metallization layer on a semiconductor substrate; 
 forming an interconnect aperture at least partially in the semiconductor substrate after the first metallization layer is formed, wherein forming an interconnect aperture includes:
 depositing a first dielectric on the first metallization layer; 
 patterning the first dielectric and forming an opening generally corresponding to the interconnect aperture; and 
 etching the first dielectric and the semiconductor substrate via the opening; 
 
 filling the interconnect aperture with a first conductive material; and 
 forming a second metallization layer over the first metallization layer, the second metallization layer being in electrical contact with the conductive material in the interconnect aperture and wherein filling the second metallization layer includes:
 depositing a second dielectric on the first dielectric and the first conductive material in the interconnect aperture; 
 forming a via in the first dielectric and the second dielectric exposing at least a portion of the first metallization layer; 
 patterning the second dielectric based on a desired profile of the second metallization layer; and 
 filling the pattern with a second conductive material, wherein the second conductive material includes a first portion in direct contact with the first conductive material in the interconnect aperture, a second portion continuous with the first portion and extending laterally away from the first portion above the first dielectric and coplanar with the patterned second dielectric material, and a third portion continuous with the second portion and filling the via to contact the first metallization layer. 
 
 
     
     
       2. The method of  claim 1  wherein:
 filling the interconnect aperture includes:
 introducing a first conductive material in the interconnect aperture; and 
 removing excess first conductive material external to the interconnect aperture; 
 
 forming a second metallization layer further includes forming a depression in the second dielectric, the depression exposing at least a portion of the first conductive material in the interconnect aperture. 
 
     
     
       3. The method of  claim 1  wherein the via is a first via, and wherein:
 filling the interconnect aperture includes:
 introducing a first conductive material in the interconnect aperture; and 
 removing excess first conductive material external to the interconnect aperture; and 
 
 forming the second metallization layer includes:
 forming a second via in the second dielectric and the first dielectric, the second via exposing at least a portion of the first conductive material in the interconnect aperture; and 
 forming a depression in the second dielectric, the depression generally corresponding to the desired profile of the second metallization layer, 
 
 wherein filling pattern with the second conductive material includes filling second via and the depression with the second conductive material. 
 
     
     
       4. The method of  claim 1  wherein:
 forming the second metallization layer includes:
 forming a depression in the pattern in the second dielectric, the depression exposing at least a portion of the conductive material in the interconnect aperture; and 
 filling the depression with the second conductive material. 
 
 
     
     
       5. The method of  claim 1  wherein the via is a first via, and wherein:
 forming the second metallization layer includes:
 depositing a dielectric on the first metallization layer and the first conductive material in the interconnect aperture; 
 forming a second via in the first and second dielectrics, the second via exposing at least a portion of the first conductive material in the interconnect aperture; and 
 filling second via with the second conductive material. 
 
 
     
     
       6. A method for fabricating a semiconductor device, comprising:
 forming a first, second, . . . , and N−2 metallization layers on a semiconductor substrate, N being a positive integer not less than 3; 
 depositing a first dielectric layer over the N−2 metallization layer and the conductive interconnect; 
 forming an interconnect aperture at least partially in the semiconductor substrate at least after the after the N−2 metallization layer is formed; 
 filling the interconnect aperture with a first conductive material; and 
 forming N−1 and N th  metallization layers after filling the interconnect aperture with the conductive material, wherein the N−1 metallization layer includes a second conductive material having a first portion in direct contact with the first conductive material in the interconnect aperture, a second portion continuous with the first portion and extending laterally away from the first portion above a first dielectric layer and coplanar with a second dielectric layer, and a third portion continuous with the second portion and filling at least one via between the N−1 metallization layer and the N−2 metallization layer. 
 
     
     
       7. The method of  claim 6  wherein the method further includes forming a conductive via directly between the N−1 metallization layer and the conductive material in the interconnect aperture. 
     
     
       8. The method of  claim 6  wherein the first conductive material in the interconnect aperture includes a first portion in direct contact with the N−1 metallization layer and a second portion in the interconnect aperture. 
     
     
       9. The method of  claim 1 , further comprising forming a third metallization layer over the second metallization layer. 
     
     
       10. The method of  claim 9  wherein forming the third metallization layer includes:
 depositing a third dielectric on the second dielectric and the second metallization layer; 
 patterning the third dielectric based on a desired profile of the third metallization layer; and 
 filling the pattern in the third dielectric with a third conductive material. 
 
     
     
       11. The method of  claim 9  wherein forming the third metallization layer includes:
 depositing a third dielectric on the second dielectric and the second metallization layer; and 
 forming at least one via in the third dielectric exposing a portion of the second metallization layer. 
 
     
     
       12. The method of  claim 6  wherein forming the N−1 metallization layer includes:
 patterning a second dielectric layer on the first dielectric layer based on a desired profile of the N−1 metallization layer; 
 forming the at least one via in the first dielectric layer and the second dielectric exposing at least a portion of the N−2 metallization layer; 
 forming a depression in the second dielectric exposing at least a portion of the conductive interconnect; and 
 filling the at least one via, the depression, and the pattern in the second dielectric with the second conductive material. 
 
     
     
       13. The method of  claim 6  wherein the at least one via is at least one first via, and wherein forming the N metallization layer includes:
 depositing a second dielectric layer over the N−1 metallization layer; 
 patterning the second dielectric layer based on a desired profile of the N metallization layer; 
 forming at least one second via in the second dielectric exposing at least a portion of the N−1 metallization layer; and 
 filling the at least one second via and the pattern in the second dielectric with the second conductive material. 
 
     
     
       14. The method of  claim 6  wherein forming the interconnect aperture includes:
 patterning the first dielectric and forming an opening generally corresponding to a desired location for the interconnect aperture; and 
 etching the first dielectric and the semiconductor substrate via the opening to form the interconnect aperture. 
 
     
     
       15. The method of  claim 14  wherein filling the interconnect aperture with the second conductive material includes:
 depositing an insulation material over the interconnect aperture; 
 depositing a seed layer over the insulation layer; 
 depositing the second conductive material over the seed layer. 
 
     
     
       16. A method for fabricating a semiconductor device, comprising:
 forming a first metallization layer on a semiconductor substrate; 
 forming an interconnect aperture at least partially in the semiconductor substrate after the first metallization layer is formed; 
 filling the interconnect aperture with a first conductive material; and 
 forming a second metallization layer over the first metallization layer and the first conductive material, wherein forming the second metallization layer includes:
 depositing a dielectric over the first metallization layer and the first conductive material in the interconnect aperture; 
 forming at least one via in the dielectric exposing a portion of the first metallization layer; 
 patterning the dielectric based on a desired profile of the second metallization layer; and 
 filling the pattern with a second conductive material, wherein the second conductive material includes a first portion in direct contact with the first conductive material in the interconnect aperture, a second portion continuous with the first portion and extending laterally away from the first portion coplanar with the patterned second dielectric material, and a third portion continuous with the second portion and filling the via to contact the first metallization layer. 
 
 
     
     
       17. The method of  claim 16  wherein filling the interconnect aperture includes:
 depositing an insulation material over the interconnect aperture; 
 forming a barrier layer over the insulation layer; and 
 forming a seed layer over the insulation layer. 
 
     
     
       18. The method of  claim 16  wherein forming the second metallization layer further includes
 forming a depression in the dielectric exposing at least a portion of the first conductive material in the interconnect aperture. 
 
     
     
       19. The method of  claim 16  wherein the dielectric is a first dielectric, and wherein the method further comprises forming a third metallization layer over the second metallization layer, wherein the forming the third metallization layer includes:
 depositing a second dielectric on the first dielectric and the second metallization layer; 
 patterning the second dielectric based on a desired profile of the second metallization layer; and 
 filling the pattern with a third conductive material.