Transmitter and shortening method thereof

Abstract

A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to generate a plurality of bit groups each of which is formed of a same number of bits, maps the outer-encoded bits to some of the bits in the bit groups, and pads zero bits to remaining bits in the bit groups, based on a predetermined shortening pattern, thereby to constitute Low Density Parity Check (LDPC) information bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the remaining bits in which zero bits are padded include some of the bit groups which are not sequentially disposed in the LDPC information bits.

What is claimed is: 
     
       1. A receiving apparatus for receiving a signal from a transmitting apparatus through a television signal communication network, the receiving apparatus being operable in a mode among a plurality of modes, the receiving apparatus comprising:
 a receiver configured to receive the signal; 
 a demodulator configured to demodulate the signal to generate values based on a 64-quadrature amplitude modulation (QAM) of the mode; 
 an inserter configured to fill a space of a predetermined size with one or more values of the values and one or more predetermined values; and 
 a decoder configured to decode values included in the space and remaining values among the values based on a low density parity check (LDPC) code, a code rate of the mode being 6/15, a code length of the mode being 16200 bits and the remaining values being corresponding to parity bits, 
 wherein the space is filled by dividing the space Tinto a plurality of group areas, determining, based on order of the mode, at least one group area to which the one of more predetermined values are inserted among the plurality of group areas and inserting the one or more predetermined values to the at least one group area, and 
 wherein the order of the mode is represented below: 
 
       
         
           
                 
                 
                 
               
                     
                 
                     
                     
                   π s (j) (0 ≤ j < N info _group) 
                 
                 
                 
                 
                 
                 
                 
                 
               
                     
                     
                   π s (0) 
                   π s (1) 
                   π s (2) 
                   π s (3) 
                   π s (4) 
                 
                     
                   N info _group 
                   π s (9) 
                   π s (10) 
                   π s (11) 
                   π s (12) 
                   π s (13) 
                 
                     
                 
                     
                   18 
                   2 
                   4 
                   5 
                   17 
                    9 
                 
                     
                     
                   8 
                   10 
                   14 
                   16 
                    0 
                 
                     
                 
                 
                 
               
                     
                   π s (j) (0 ≤ j < N info _group) 
                 
                 
                 
                 
                 
                 
                 
               
                     
                     
                   π s (5)  
                   π s (6) 
                   π s (7) 
                   π s (8) 
                 
                     
                   N info _group 
                   π s (14) 
                   π s (15) 
                   π s (16) 
                   π s (17) 
                 
                     
                 
                     
                   18 
                   7 
                   1 
                   6 
                   15 
                 
                     
                     
                   11 
                   13 
                   12 
                     3, 
                 
                     
                 
             
                
               
               
                
               
            
             
                
                
                
                
                
                
               
            
             
                
               
            
             
                
                
                
                
                
                
               
            
           
         
         where π s (j) represents an index of a group for padding in a j-th order among the plurality of bit group areas and N info_group  represents a number of the plurality of bit group areas. 
       
     
     
       2. The receiving apparatus of  claim 1 , wherein the inserter is configured to calculate a number of group areas in which all values are inserted with the predetermined values bed on a following equation: 
       
         
           
             
               
                 
                   N 
                   pad 
                 
                 = 
                 
                   ⌊ 
                   
                     
                       
                         K 
                         ldpc 
                       
                       - 
                       
                         N 
                         outer 
                       
                     
                     360 
                   
                   ⌋ 
                 
               
               , 
             
           
         
         where N pad  represents the number of the group areas, K ldpc  represents the predetermined size, and N outer  represents a number of the one or more values. 
       
     
     
       3. The receiving apparatus of  claim 2 , wherein the inserter is configured to pad the one or more predetermined values to π s (0)-th group area, a π s (1)-th group area, . . . , a π s (N pad −1)-th group area among the plurality of group areas based on the order. 
     
     
       4. The receiving apparatus of  claim 3 , wherein the inserter is configured to additionally pad the one or more predetermined values to K ldpc −N outer −360×N pad  zero bits from a first value of a π s (N pad )-th group area based on the order. 
     
     
       5. A transmitting apparatus for transmitting a signal to a receiving apparatus through a television signal communication network, the transmitting apparatus comprising:
 at least one processor configured to:
 fill information bits with input bits and one or more zero padding bits, if a number of the input bits is less than a number of the information bits, 
 encode the information bits based on a low density parity check (LDPC) code to generate parity bits, a code rate of the LDPC code being 6/15 and a code length of the LDPC code being 16200 bits, 
 interleave the parity bits, 
 remove the one or more zero padding bits among the information bits, and 
 map the input bits and the interleaved parity bits onto constellation points for 64-quadrature amplitude modulation (QAM); and 
 
 a transmitter configured to transmit the signal which is generated based on the constellation points, 
 wherein the informations bits is filled by dividing the information bits into a plurality of bit groups, determining at least one bit group to which the one or more zero padding bits are padded among the plurality of bit groups based on a zero padding order, and padding the one or more zero padding bits to the determined bit group, and 
 wherein the zero padding order is represented below: 
 
       
         
           
                 
                 
               
                     
                 
                     
                   π s (j) (0 ≤ j < N info _group) I 
                 
                 
                 
                 
                 
                 
                 
                 
                 
                 
                 
               
                     
                   π s (0) 
                   π s (1) 
                   π s (2) 
                   π s (3) 
                   π s (4) 
                   π s (5) 
                   π s (6) 
                   π s (7) 
                   π s (8) 
                 
                   N info _group 
                   π s (9) 
                   π s (10) 
                   π s (11) 
                   π s (12) 
                   π s (13) 
                   π s (14) 
                   π s (15) 
                   π s (16) 
                   π s (17) 
                 
                     
                 
                 
                 
                 
                 
                 
                 
                 
                 
                 
                 
               
                   18 
                   2 
                   4 
                   5 
                   17 
                   9 
                   7 
                   1 
                   6 
                   15 
                 
                     
                   8 
                   10 
                   14 
                   16 
                   0 
                   11 
                   13 
                   12 
                   3 
                 
                     
                 
             
                
                
               
            
             
                
                
                
               
            
             
                
                
                
               
            
           
         
         where π s (j) represents ara index of a bit group for packing in a j-th order among the plurality of bit groups and N info_group  represents a number of the plurality of bit groups. 
       
     
     
       6. The transmitting apparatus of  claim 5 , wherein the at least one processor is configured to calculate a number of bit group to which all bits are padded with the one or more zero padding bits based on a following equation:
     N   pad   =└K   ldpc   −N   outer /360┘,
 
 where Npad represents the number of the bit group to which all bits are padded with the one or more zero padding bits, Kldpc represents the number of the information hits, and Nouter represents the number of the input bits. 
 
     
     
       7. The transmitting apparatus of  claim 6 , wherein the at least one processor is configured to pad the one or more zero padding bits to all bits of a πS(0)-th bit group, a πS(1)-th bit group, . . . , a πS(Npad−1)-th bit group among the plurality of bit groups based on the zero padding order. 
     
     
       8. The transmitting apparatus of  claim 7 , wherein the at least one processor is configured to additionally pad Kldpc−Nouter−360×Npad zero padding bits from a first bit of a πs(Npad)-th bit group based on the order.