Semiconductor device having a dummy gate with a cut-out opening between adjacent fins and methods of forming the same

Abstract

Semiconductor device and fabrication method are provided. A plurality of spaced-apart fins is formed on a substrate. A dummy gate structure is formed across the fins over the substrate. A first interlayer dielectric layer is formed on the substrate and on a sidewall of the dummy gate structure, and a top of the first interlayer dielectric layer is lower than a top of the dummy gate structure and higher than a top of the fins. A cut-out opening, according to a cut-out pattern, is formed through the dummy gate structure and between adjacent fins. A second interlayer dielectric layer is formed on the first interlayer dielectric layer and fills in the cut-out opening.

What is claimed is: 
     
       1. A method of forming a semiconductor device, comprising:
 providing a substrate; 
 forming a plurality of spaced-apart fins on the substrate; 
 forming a dummy gate structure across the fins over the substrate; 
 forming a first interlayer dielectric layer on the substrate and on a sidewall of the dummy gate structure, wherein a top of the first interlayer dielectric layer is lower than a top of the dummy gate structure and higher than the top of the fins; 
 forming a cut-out opening, according to a cut-out pattern, passing through the dummy gate structure and between adjacent fins; 
 forming an insulating layer on the sidewall of the dummy gate structure and on a sidewall of the cut-out opening, wherein the insulating layer includes a first portion on the top of the first interlayer dielectric layer and located at a side of the dummy gate structure away from the cut-out opening in a direction perpendicular to an extension direction of the plurality of spaced-apart fins and a second portion on the sidewall of the cut-out opening; and 
 forming a second interlayer dielectric layer on the first interlayer dielectric layer and filling in the cut-out opening with the second interlayer dielectric layer. 
 
     
     
       2. The method according to  claim 1 , prior to forming the dummy gate structure, further including:
 forming an isolation structure on the substrate between adjacent fins and covering a sidewall portion of each fin, wherein the cut-out opening passing through the dummy gate structure exposes a portion of the isolation structure. 
 
     
     
       3. The method according to  claim 1 , wherein the cut-out opening is formed by a dry etching that uses carbon tetrafluoride, sulfur hexafluoride plus nitrogen and oxygen as an etching atmosphere, wherein the carbon tetrafluoride has a flow rate in a range of 50 sccm-2005 sccm, the sulfur hexafluoride has a flow rate in a range of 5 sccm-500 sccm, the nitrogen has a flow rate in a range of 6 sccm-300 sccm, the oxygen has a flow rate in a range of 1 sccm-250 sccm, an etching pressure is in a range of 1 mtorr-150 mtorr, an etching time is in a range of 10 s-2000 s, a voltage is in a range of 50 V-300 V, and a power is in a range of 200 W-500 W. 
     
     
       4. The method according to  claim 1 , wherein:
 the insulating layer is formed before forming the second interlayer dielectric layer. 
 
     
     
       5. The method according to  claim 4 , wherein the insulating layer includes a single-layer structure or a multi-layer structure. 
     
     
       6. The method according to  claim 5 , wherein when the single-layer structure is used for the insulating layer, the insulating layer is made of a material including silicon nitride, silicon oxynitride, or silicon carbonitride. 
     
     
       7. The method according to  claim 1 , wherein the first interlayer dielectric layer is made of a material including silicon oxide, silicon carbide, silicon oxynitride, silicon nitride, or a combination thereof. 
     
     
       8. The method according to  claim 7 , wherein the first interlayer dielectric layer is formed by a method including a chemical vapor deposition or an atomic layer deposition. 
     
     
       9. The method according to  claim 1 , wherein the second interlayer dielectric layer is made of a material including silicon oxide, silicon carbide, silicon oxynitride, silicon nitride, or a combination thereof. 
     
     
       10. The method according to  claim 9 , wherein the second interlayer dielectric layer is formed by a method including a chemical vapor deposition, an atomic layer deposition, or a physical vapor deposition. 
     
     
       11. A method of forming a semiconductor device, comprising:
 providing a substrate; 
 forming a plurality of spaced-apart fins on the substrate; 
 forming a dummy gate structure across the fins over the substrate; 
 forming a first interlayer dielectric layer on the substrate and on a sidewall of the dummy gate structure, wherein a top of the first interlayer dielectric layer is lower than a top of the dummy gate structure and higher than the top of the fins; 
 forming a cut-out opening, according to a cut-out pattern, passing through the dummy gate structure and between adjacent fins; 
 forming an insulating layer on the sidewall of the dummy gate structure and on the sidewall of the cut-out opening before forming a second interlayer dielectric layer; and 
 forming the second interlayer dielectric layer on the first interlayer dielectric layer and filling in the cut-out opening with the second interlayer dielectric layer, wherein 
 the insulating layer includes a multi-layer structure; and 
 when the multi-layer structure is used for the insulating layer, the insulating layer is made of a combination of one or more of silicon nitride, silicon oxynitride, and silicon carbonitride. 
 
     
     
       12. A semiconductor device, comprising:
 a substrate; 
 a plurality of spaced-apart fins on the substrate; 
 a dummy gate structure across the fins over the substrate, wherein the dummy gate structure includes a cut-out opening between adjacent fins; 
 a first interlayer dielectric layer on the substrate and on a sidewall of the dummy gate structure, wherein a top of the first interlayer dielectric layer is lower than a top of the dummy gate structure and higher than a top of the fins; 
 an insulating layer formed on the sidewall of the dummy gate structure and on a sidewall of the cut-out opening, wherein the insulating layer includes a first portion on the top of the first interlayer dielectric layer and located at a side of the dummy gate structure away from the cut-out opening in a direction perpendicular to an extension direction of the plurality of spaced-apart fins and a second portion on the sidewall of the cut-out opening; and 
 a second interlayer dielectric layer on the first interlayer dielectric layer and filling in the cut-out opening through the dummy gate structure between the adjacent fins. 
 
     
     
       13. The device according to  claim 12 , further including:
 an isolation structure formed on the substrate between adjacent fins and covering a sidewall portion of each fin, wherein:
 the dummy gate structure is formed on the isolation structure, and 
 the second interlayer dielectric layer formed on the first interlayer dielectric layer is further formed on the isolation structure between adjacent fins. 
 
 
     
     
       14. The device according to  claim 12 , wherein the insulating layer includes a single-layer structure or a multi-layer structure. 
     
     
       15. The device according to  claim 12 , wherein the insulating layer is made of a material including silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof. 
     
     
       16. The device according to  claim 12 , wherein the first interlayer dielectric layer is made of a material including silicon oxide, silicon carbide, silicon oxynitride, silicon nitride, or a combination thereof. 
     
     
       17. The device according to  claim 12 , wherein the second interlayer dielectric layer is made of a material including silicon oxide, silicon carbide, silicon oxynitride, silicon nitride, or a combination thereof. 
     
     
       18. The device according to  claim 12 , wherein a top of the second interlayer dielectric layer is co-planar with the top of the dummy gate structure. 
     
     
       19. The device according to  claim 12 , wherein a top of the second interlayer dielectric layer is coplanar with a top of a mask layer formed over the dummy gate structure.