Optimized convolution for received XOR encrypted data streams
Abstract
A receiver apparatus and method for optimized decryption and despreading of a very low frequency (VLF) bitstream is disclosed. In embodiments, the receiver includes antenna elements for receiving a transmission security (TRANSEC) encoded bitstream associated with an uncertainty window size and a spread factor. The receiver includes cryptographic processors that, when the spread factor is sufficiently large, select key section numbers A and data section numbers B based on the window size and spread factor. The cryptographic processors generate an output sequence of correlation windows, each correlation window associated with a symbol of the bitstream, via pipelined sectional mirrored-key convolution based on a key section number A and data section number B chosen to optimize performance (e.g., processor performance, memory performance).
Claims
exact text as granted — not AI-modifiedWe claim:
1. A receiver apparatus, comprising:
at least one antenna element configured to receive at least one transmission security (TRANSEC) encoded bitstream, the bitstream associated with an output window size W and a spreading factor S, where W and S are integers; and
one or more cryptographic processors configured to, when the spreading factor S exceeds a spreading threshold:
select one or more key section numbers A, each key section number A corresponding to a number of key sections of a decryption key, where A is an integer divisor of the spreading factor S;
select one or more data section numbers B based on the output window size W and the selected key section number A, where B is an integer corresponding to a number of data sections of the bitstream; and
generate an output sequence of correlation windows based on at least one pipelined sectional convolution of the selected key section number A and the selected data section number B, each correlation window associated with a bit of the bitstream.
2. The receiver apparatus of claim 1 , wherein the one or more cryptographic processors are configured to:
select one or more fast Fourier transforms (FFT) corresponding to a size N based on at least one of a group including the output window size W, the spreading factor S, and the selected key section number A, where N is an integer; and
generate the output sequence of correlation windows based on at least one pipelined sectional convolution comprising A fast Fourier transforms of size N and B inverse fast Fourier transforms of size N, wherein A is the selected key section number and B is the selected data section number.
3. The receiver apparatus of claim 2 , further comprising:
one or more signal processors in communication with the one or more cryptographic processors,
the at least one pipelined sectional convolution including at least one operation executed by the one or more signal processors.
4. The receiver apparatus of claim 2 , wherein the one or more cryptographic processors are configured to generate the output sequence of correlation windows based on at least one pipelined sectional convolution comprising at least one of:
A real key fast Fourier transforms of size N; or
A complex data fast Fourier transforms of size N;
wherein A is the selected key section number.
5. The receiver apparatus of claim 1 , wherein the one or more cryptographic processors are configured to:
determine a finite set of all possible key section numbers and all possible data section numbers; and
select from the determined finite set of all possible key section numbers and all possible data section numbers 1) an optimal key section number A and 2) an optimal data section number B.
6. The receiver apparatus of claim 5 , wherein the one or more cryptographic processors are configured to select one or more of the optimal key section number A and the optimal data section number B to minimize usage of the one or more cryptographic processors.
7. The receiver apparatus of claim 5 , further comprising:
at least one memory operatively coupled to the one or more cryptographic processors, the memory configured to store the output sequence; and
the one or more cryptographic processors are configured to select one or more of the optimal key section number A and the optimal data section number B to minimize a portion of the memory corresponding to the storing of the output sequence.
8. A method for optimizing a decryption and despreading of a received bitstream, the method comprising:
receiving, via one or more antenna elements, at least one transmission security (TRANSEC) encoded bitstream, the bitstream associated with an output window size W and a spreading factor S, where W and S are integers;
determining, via one or more cryptographic processors in communication with the antenna elements, whether the spreading factor S exceeds a spreading threshold;
when the spreading factor S exceeds the spreading threshold, selecting, via the one or more cryptographic processors:
one or more key section numbers A, each key section number A corresponding to a number of key sections of a decryption key, where A is an integer divisor of the spreading factor S; and
one or more data section numbers B based on the output window size W and the selected key section number A, where B is an integer corresponding to a number of data sections of the bitstream; and
generating, via the one or more cryptographic processors, an output sequence of correlation windows based on at least one pipelined sectional convolution of the selected key section number A and the selected data section number B, each correlation window associated with a bit of the bitstream.
9. The method of claim 8 , wherein, selecting, via the one or more cryptographic processors, one or more key section numbers A and one or more data section numbers B includes:
selecting, via the one or more cryptographic processors, one or more fast Fourier transforms (FFT) corresponding to a size N based on at least one of a group including the output window size W, the spreading factor S, and the selected key section number A, where N is an integer.
10. The method of claim 9 , wherein generating, via the one or more cryptographic processors, an output sequence of correlation windows based on at least one pipelined sectional convolution of the selected key section number A and the selected data section number B, includes:
generating, via the one or more cryptographic processors, an output sequence of correlation windows based on at least one pipelined sectional convolution comprising A fast Fourier transforms of size N and B inverse fast Fourier transforms of size N, wherein A is the selected key section number and B is the selected data section number.
11. The method of claim 10 , wherein generating, via the one or more cryptographic processors, an output sequence of correlation windows based on at least one pipelined sectional convolution comprising A fast Fourier transforms of size N and B inverse fast Fourier transforms of size N, wherein A is the selected key section number and B is the selected data section number, includes:
generating, via the one or more cryptographic processors, an output sequence of correlation windows based on at least one pipelined sectional convolution, the pipelined sectional convolution including at least one operation executed by one or more signal processors in communication with the one or more cryptographic processors.
12. The method of claim 10 , wherein the at least one pipelined sectional convolution comprises at least one of:
A real key fast Fourier transforms of size N; or
A complex data fast Fourier transforms of size N;
wherein A is the selected key section number.
13. The method of claim 8 , wherein generating, via the one or more cryptographic processors, an output sequence of correlation windows based on at least one pipelined sectional convolution of the selected key section number A and the selected data section number B includes:
determining a first set of all possible key section numbers;
determining a second set of all possible data section numbers;
selecting from the first set of all possible key section numbers an optimal key section number A; and
selecting from the second set of all possible data section numbers an optimal data section number B.
14. The method of claim 13 , wherein:
selecting from the first set of all possible key section numbers the optimal key section number A includes selecting the optimal key section number A to minimize usage of the one or more cryptographic processors; and
wherein selecting from the second set of all possible data section numbers the optimal data section number B includes selecting the optimal data section number B to minimize usage of the one or more cryptographic processors.
15. The method of claim 13 , wherein:
selecting from the first set of all possible key section numbers the optimal key section number A includes selecting the optimal key section number A to minimize memory usage; and
wherein selecting from the second set of all possible data section numbers the optimal data section number B includes selecting the optimal data section number B to minimize memory usage.Join the waitlist — get patent alerts
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