Memory controller with programmable atomic operations

Abstract

A memory controller circuit is disclosed which is coupleable to a first memory circuit, such as DRAM, and includes: a first memory control circuit to read from or write to the first memory circuit; a second memory circuit, such as SRAM; a second memory control circuit adapted to read from the second memory circuit in response to a read request when the requested data is stored in the second memory circuit, and otherwise to transfer the read request to the first memory control circuit; predetermined atomic operations circuitry; and programmable atomic operations circuitry adapted to perform at least one programmable atomic operation. The second memory control circuit also transfers a received programmable atomic operation request to the programmable atomic operations circuitry and sets a hazard bit for a cache line of the second memory circuit.

It is claimed: 
     
       1. A memory controller circuit coupleable to a first memory circuit, the memory controller comprising:
 a first memory control circuit coupleable to the first memory circuit, the first memory control circuit adapted to read or load requested data from the first memory circuit in response to a read request and to write or store requested data to the first memory circuit in response to a write request; 
 programmable atomic operations circuitry coupled to the first memory control circuit, the programmable atomic operations circuitry adapted to perform at least one programmable atomic operation of a plurality of programmable atomic operations in response to an atomic operation request designating the at least one programmable atomic operation; 
 a second memory circuit; and 
 a second memory control circuit coupled to the second memory circuit and to the first memory control circuit, the second memory control circuit adapted, in response to the atomic operation request designating the at least one programmable atomic operation and a memory address, to read or load the requested data from the second memory circuit when the requested data is stored in the second memory circuit, to transfer the atomic operation request designating the at least one programmable atomic operation to the programmable atomic operations circuitry, to set a hazard bit stored in a memory hazard register corresponding to the memory address, and following receipt of data resulting from the at least one programmable atomic operation, to write the resulting data from the programmable atomic operation in the second memory circuit and reset or clear the set hazard bit. 
 
     
     
       2. The memory controller circuit of  claim 1 , wherein the atomic operation request designating the at least one programmable atomic operation comprises a physical memory address, a programmable atomic operations identifier, and at least one thread state register value, wherein the programmable atomic operations circuitry further comprises at least one register storing thread state information, and wherein the programmable atomic operations circuitry is further adapted, in response to receiving the atomic operation request designating the at least one programmable atomic operation, to initialize the at least one register with the physical memory address, any data corresponding to the memory address, and the at least one thread state register value. 
     
     
       3. The memory controller circuit of  claim 1 , further comprising:
 predetermined atomic operations circuitry adapted to perform at least one predetermined atomic operation of a plurality of predetermined atomic operations in response to an atomic operation request designating the at least one predetermined atomic operation. 
 
     
     
       4. The memory controller circuit of  claim 3 , wherein the second memory control circuit is further adapted to write resulting data from the predetermined atomic operation in the second memory circuit and, following writing of the resulting data, to reset or clear the set hazard bit. 
     
     
       5. The memory controller circuit of  claim 3 , wherein the plurality of predetermined atomic operations comprises at least two predetermined atomic operations selected from the group consisting of: Fetch-and-AND, Fetch-and-OR, Fetch-and-XOR, Fetch-and-Add, Fetch-and-Subtract, Fetch-and-Increment, Fetch-and-Decrement, Fetch-and-Minimum, Fetch-and-Maximum, Fetch-and-Swap, Compare-and-Swap, and combinations thereof. 
     
     
       6. The memory controller circuit of  claim 1 , wherein the programmable atomic operations circuitry comprises:
 an instruction cache storing a plurality of processor instructions corresponding to the at least one programmable atomic operation; 
 an execution queue storing a thread identifier corresponding to the programmable atomic operation; 
 a core control circuit coupled to the instruction cache and to the execution queue, the core control circuit adapted, in response to the thread identifier corresponding to the programmable atomic operation, to select a starting or next instruction or instruction address in the instruction cache for execution of the programmable atomic operation; and 
 a processor core adapted to execute at least one instruction for the programmable atomic operation and to generate resulting data. 
 
     
     
       7. The memory controller circuit of  claim 6 , wherein the programmable atomic operations circuitry further comprises:
 a memory controller interface circuit coupled to the processor core to receive the resulting data and to transfer the resulting data to the second memory control circuit to write the resulting data to the second memory circuit; and 
 at least one data buffer to store operand data and interim results generated from executing the at least one instruction for the programmable atomic operation. 
 
     
     
       8. The memory controller circuit of  claim 6 , wherein the programmable atomic operations circuitry further comprises:
 a network command queue coupled to the processor core, the network command queue storing the resulting data; and 
 a network communication interface coupled to the network command queue and coupleable to a communication network, the network communication interface adapted to prepare and transmit a response data packet having the resulting data on the communication network. 
 
     
     
       9. The memory controller circuit of  claim 6 , wherein the processor core is further adapted to execute a store and clear lock instruction to generate an atomic write request to the second memory control circuit, the atomic write request having the resulting data and a designation to reset or clear the set hazard bit following writing of the resulting data to the second memory circuit. 
     
     
       10. The memory controller circuit of  claim 6 , wherein the processor core is further adapted to execute an atomic return instruction to reset or clear the set hazard bit following writing of the resulting data to the second memory circuit. 
     
     
       11. The memory controller circuit of  claim 1 , wherein the programmable atomic operations circuitry is adapted to perform the at least one programmable atomic operation selected from the group consisting of: user-defined atomic operations, multi-cycle operations, floating point operations, multi-instruction operations, arithmetic operations, logic operations, control flow decisions, and combinations thereof. 
     
     
       12. The memory controller circuit of  claim 1 , further comprising:
 a write merge circuit adapted to write or store data read from the first memory circuit to the second memory circuit. 
 
     
     
       13. The memory controller circuit of  claim 1 , wherein the second memory control circuit is further adapted to transfer the atomic operation request designating the at least one programmable atomic operation to the first memory control circuit when the requested data is not stored in the second memory circuit. 
     
     
       14. The memory controller circuit of  claim 1 , wherein the second memory control circuit is further adapted to write or store data to the second memory circuit in response to the write request or in response to the atomic operation request. 
     
     
       15. The memory controller circuit of  claim 1 , wherein the second memory control circuit is further adapted, in response to the write request, the write request having write data and designating a memory address in the second memory circuit, to set the hazard bit stored in the memory hazard register corresponding to the memory address, to transfer current data stored at the memory address to the first memory control circuit to write the current data to the first memory circuit, to overwrite the current data in the second memory circuit with the write data and, following writing or storing the write data to the second memory circuit at the memory address, to reset or clear the set hazard bit. 
     
     
       16. The memory controller circuit of  claim 1 , wherein the first memory control circuit comprises:
 a plurality of memory bank request queues storing a plurality of read or write requests to the first memory circuit; 
 a scheduler circuit coupled to the plurality of memory bank request queues, the scheduler adapted to select a read or write request of the plurality of read or write requests from the plurality of memory bank request queues and to schedule the selected read or write request for access to the first memory circuit; and 
 a first memory access control circuit coupled to the scheduler, the first memory access control circuit adapted to read or load data from the first memory circuit and to write or store data to the first memory circuit. 
 
     
     
       17. The memory controller circuit of  claim 16 , wherein the first memory control circuit further comprises:
 a plurality of memory request queues storing a plurality of memory requests; 
 a request selection multiplexer to select a memory request from the plurality of memory request queues; 
 a plurality of memory data queues storing data corresponding to the plurality of memory requests; and 
 a data selection multiplexer to select data from the plurality of memory data queues, the selected data corresponding to the selected memory request. 
 
     
     
       18. The memory controller circuit of  claim 1 , wherein the second memory control circuit comprises:
 a network request queue storing the read request or the write request; 
 an atomic operation request queue storing the atomic operation request designating the at least one programmable atomic operation; 
 an inbound request multiplexer couple to the network request queue and to the atomic operation request queue to select a request from the network request queue or the atomic operation request queue; 
 a memory hazard control circuit having the memory hazard register; and 
 a second memory access control circuit coupled to the memory hazard control circuit and to the inbound request multiplexer, the second memory access control circuit adapted to read or load data from the second memory circuit or to write or store data to the second memory circuit in response to the selected request, and to signal the memory hazard control circuit to set or clear the hazard bit stored in the memory hazard register. 
 
     
     
       19. The memory controller circuit of  claim 18 , wherein the second memory control circuit further comprises:
 a delay circuit coupled to the second memory access control circuit; and 
 an inbound control multiplexer to select an inbound network request which requires accessing the first memory circuit or to select a cache eviction request from the second memory circuit when a cache line of the second memory circuit contains data which is to be written to the first memory circuit prior to being overwritten by data from a read request or a write request. 
 
     
     
       20. The memory controller circuit of  claim 1 , wherein the programmable atomic operations circuitry comprises:
 a processor circuit coupled to the first or second memory control circuit through a communication bus. 
 
     
     
       21. A memory controller circuit coupleable to a first memory circuit, the memory controller comprising:
 a first memory control circuit coupleable to the first memory circuit, the first memory control circuit adapted to read or load requested data from the first memory circuit in response to a read request and to write or store requested data to the first memory circuit in response to a write request; 
 programmable atomic operations circuitry coupled to the first memory control circuit, the programmable atomic operations circuitry adapted to perform at least one programmable atomic operation in response to an atomic operation request designating the at least one programmable atomic operation, the at least one programmable atomic operation selected from the group consisting of: user-defined atomic operations, multi-cycle operations, floating point operations, multi-instruction operations, arithmetic operations, logic operations, control flow decisions, and combinations thereof; 
 a second memory circuit; 
 a second memory control circuit coupled to the second memory circuit and to the first memory control circuit, the second memory control circuit adapted, in response to the atomic operation request designating the at least one programmable atomic operation and a memory address, to read or load the requested data from the second memory circuit when the requested data is stored in the second memory circuit, to transfer the atomic operation request designating the at least one programmable atomic operation to the first memory control circuit when the requested data is not stored in the second memory circuit, to transfer the atomic operation request designating the at least one programmable atomic operation to the programmable atomic operations circuitry, to set a hazard bit stored in a memory hazard register corresponding to the memory address, and following receipt of data resulting from the at least one programmable atomic operation, to write the resulting data from the programmable atomic operation in the second memory circuit and reset or clear the set hazard bit. 
 
     
     
       22. The memory controller circuit of  claim 21 , further comprising:
 predetermined atomic operations circuitry adapted to perform at least one predetermined atomic operation in response to an atomic operation request designating the at least one predetermined atomic operation, the at least one predetermined atomic operation selected from the group consisting of: Fetch-and-AND, Fetch-and-OR, Fetch-and-XOR, Fetch-and-Add, Fetch-and-Subtract, Fetch-and-Increment, Fetch-and-Decrement, Fetch-and-Minimum, Fetch-and-Maximum, Fetch-and-Swap, Compare-and-Swap, and combinations thereof; and 
 wherein the second memory control circuit is further adapted to write resulting data from the predetermined atomic operation in the second memory circuit and, following writing of the resulting data, to reset or clear the set hazard bit. 
 
     
     
       23. The memory controller circuit of  claim 21 , wherein the programmable atomic operations circuitry comprises:
 an instruction cache storing a plurality of processor instructions corresponding to the at least one programmable atomic operation; 
 an execution queue storing a thread identifier corresponding to the programmable atomic operation; 
 a core control circuit coupled to the instruction cache and to the execution queue, the core control circuit adapted, in response to the thread identifier corresponding to the programmable atomic operation, to select a starting or next instruction or instruction address in the instruction cache for execution of the programmable atomic operation; and 
 a processor core adapted to execute at least one instruction for the programmable atomic operation and to generate resulting data. 
 
     
     
       24. The memory controller circuit of  claim 21 , wherein the second memory control circuit is further adapted, in response to the write request, the write request having write data and designating a memory address in the second memory circuit, to set the hazard bit stored in the memory hazard register corresponding to the memory address, to transfer current data stored at the memory address to the first memory control circuit to write the current data to the first memory circuit, to overwrite the current data in the second memory circuit with the write data and, following writing or storing the write data to the second memory circuit at the memory address, to reset or clear the set hazard bit. 
     
     
       25. The memory controller circuit of  claim 21 , wherein the second memory control circuit comprises:
 a network request queue storing the read request or the write request; 
 an atomic operation request queue storing the atomic operation request designating the at least one programmable atomic operation; 
 an inbound request multiplexer couple to the network request queue and to the atomic operation request queue to select a request from the network request queue or the atomic operation request queue; 
 a memory hazard control circuit having the memory hazard register; and 
 a second memory access control circuit coupled to the memory hazard control circuit and to the inbound request multiplexer, the second memory access control circuit adapted to read or load data from the second memory circuit or to write or store data to the second memory circuit in response to the selected request, and to signal the memory hazard control circuit to set or clear the set hazard bit stored in the memory hazard register. 
 
     
     
       26. The memory controller circuit of  claim 25 , wherein the second memory control circuit further comprises:
 a delay circuit coupled to the second memory access control circuit; and 
 an inbound control multiplexer to select an inbound network request which requires accessing the first memory circuit or to select a cache eviction request from the second memory circuit when a cache line of the second memory circuit contains data which is to be written to the first memory circuit prior to being overwritten by data from a read request or a write request. 
 
     
     
       27. A memory controller coupleable to a first memory circuit, the memory controller comprising:
 a first memory control circuit coupleable to the first memory circuit, the first memory control circuit adapted to read or load requested data from the first memory circuit in response to a read request and to write or store requested data to the first memory circuit in response to a write request; 
 a second memory circuit; 
 predetermined atomic operations circuitry adapted to perform at least one predetermined atomic operation; 
 programmable atomic operations circuitry adapted to perform at least one programmable atomic operation of a plurality of programmable atomic operations in response to an atomic operation request designating the at least one programmable atomic operation; and 
 a second memory control circuit coupled to the second memory circuit, the second memory control circuit comprising: 
 at least one input request queue storing the read request or the write request; 
 a memory hazard control circuit having a memory hazard register; and 
 a second memory access control circuit coupled to the second memory circuit and to the first memory control circuit, the second memory access control circuit adapted, in response to the atomic operation request designating the at least one programmable atomic operation and a memory address, to read or load the requested data from the second memory circuit when the requested data is stored in the second memory circuit, and to write or store data to the second memory circuit, to transfer the atomic operation request designating the at least one programmable atomic operation to the programmable atomic operations circuitry, to set a hazard bit stored in the memory hazard register corresponding to the memory address, to write resulting data from the at least one programmable atomic operation to the second memory circuit and, following writing of the resulting data, to reset or clear the set hazard bit.