Reference generation circuit for maintaining temperature-tracked linearity in amplifier with adjustable high-frequency gain

Abstract

Equalizing an input signal according to a receiver equalizer peaking circuit having a capacitor FET (CFET) providing a capacitive value and a resistor FET (RFET) providing a resistive value, generating a capacitor control voltage at a gate of the CFET using a capacitor controller DAC based on a first reference voltage, and a RFET control voltage at a gate of the RFET using a resistor controller DAC based on a second reference voltage, generating the first reference voltage using a replica input FET, the first reference voltage varying according to a threshold voltage (Vt) of an input FET, providing the first reference voltage to the capacitor controller DAC, generating the second reference voltage using a replica RFET, the second reference voltage varying with respect to the first reference voltage and a Vt of the replica of the RFET, and providing the second reference voltage to the resistor controller DAC.

I claim: 
     
       1. An apparatus comprising:
 a receiver equalizer peaking circuit having a capacitor Field Effect Transistor (CFET) providing a capacitive value and a resistor FET (RFET) providing a resistive value; 
 a controller circuit comprising a capacitor controller digital-to-analog converter (DAC) configured to provide a CFET control voltage to the CFET based on a first reference voltage, and a resistor controller DAC configured to provide a RFET control voltage to a gate of the RFET based on a second reference voltage; 
 a reference generation circuit configured to generate the first and second reference voltages, the reference generation circuit comprising:
 a replica input FET configured to generate the first reference voltage that varies at least according to a threshold voltage (Vt) of an input FET, the replica input FET configured to provide the first reference voltage to the capacitor controller DAC to maintain temperature-tracked DAC linearity; 
 a replica RFET configured to generate the second reference voltage that varies with respect to (i) the first reference voltage and (ii) a Vt of the RFET, and to provide the second reference voltage to the resistor controller to maintain the temperature-tracked DAC linearity. 
 
 
     
     
       2. The apparatus of  claim 1 , wherein the first reference voltage further varies responsive to variations in a common mode voltage of an input signal received at the input FET. 
     
     
       3. The apparatus of  claim 1 , wherein the replica RFET is part of a voltage divider circuit, and wherein the second reference voltage is generated at an output tap of the voltage divider circuit. 
     
     
       4. The apparatus of  claim 3 , wherein the replica RFET has a gate input connected to the output tap of the voltage divider circuit. 
     
     
       5. The apparatus of  claim 3 , wherein the voltage divider circuit is a replica of a voltage divider in the resistor controller DAC. 
     
     
       6. The apparatus of  claim 3 , wherein the voltage divider circuit comprise at least one passive resistance element between the output tap and the RFET, the passive resistive element providing a voltage drop at least in part to increase a resolution of the resistor controller DAC. 
     
     
       7. The apparatus of  claim 1 , wherein the replica input FET is a scaled version of the input FET. 
     
     
       8. The apparatus of  claim 1 , wherein the CFET control voltage and the RFET control voltage are variable output voltages that vary according to variations in the first and second reference voltages, respectively. 
     
     
       9. The apparatus of  claim 1 , wherein the second reference voltage further tracks the Vt of the input FET. 
     
     
       10. The apparatus of  claim 1 , wherein the CFET is connected in a varactor diode configuration, and wherein the CFET control voltage is provided to a gate of the CFET. 
     
     
       11. A method comprising:
 equalizing an input signal according to a receiver equalizer peaking circuit having a capacitor FET (CFET) providing a capacitive value and a resistor FET (RFET) providing a resistive value; 
 generating a capacitor control voltage at a gate of the CFET using a capacitor controller DAC based on a first reference voltage, and a RFET control voltage at a gate of the RFET using a resistor controller DAC based on a second reference voltage; 
 generating the first reference voltage using a replica input FET, the first reference voltage varying according to a threshold voltage (Vt) of an input FET; 
 providing the first reference voltage to the capacitor controller DAC to maintain temperature-tracked DAC linearity; 
 generating the second reference voltage using a replica RFET, the second reference voltage varying with respect to (i) the first reference voltage and (ii) a Vt of the replica of the RFET; and 
 providing the second reference voltage to the resistor controller DAC to maintain the temperature-tracked DAC linearity. 
 
     
     
       12. The method of  claim 11 , wherein the first reference voltage further varies responsive to variations in a common mode voltage of an input signal received at the input FET. 
     
     
       13. The method of  claim 11 , wherein generating the second reference voltage comprises generating a current through a voltage divider circuit containing the replica RFET, wherein the current varies responsive at least in part to variations in resistance of the replica RFET, and wherein the second reference voltage is generated at an output tap of the voltage divider circuit. 
     
     
       14. The method of  claim 13 , wherein the replica RFET has a gate input connected to the output tap of the voltage divider circuit. 
     
     
       15. The method of  claim 13 , wherein the voltage divider circuit is a replica of a voltage divider in the resistor controller DAC. 
     
     
       16. The method of  claim 13 , wherein the output tap of the voltage divider circuit is separated from the replica RFET by at least one passive resistance element, the passive resistance element generating a voltage drop at least in part for increasing a resolution of the resistor controller DAC. 
     
     
       17. The method of  claim 11 , wherein the replica input FET is a scaled version of the input FET. 
     
     
       18. The method of  claim 11 , wherein the first reference voltage is process-dependent with respect to the input FET. 
     
     
       19. The method of  claim 11 , wherein the second reference voltage is process-dependent with respect to the input FET and the RFET. 
     
     
       20. The method of  claim 11 , wherein the CFET comprises a varactor diode.