System and method for reducing cell area and current leakage in anti-fuse cell array

Abstract

A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first CPODE associated with a first program word line, the second polysilicon line intersecting the first active region and the first CPODE intersecting the second active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second CPODE intersecting the first active region to form a cross-arrangement of CPODE.

What is claimed is: 
     
       1. A memory device comprising:
 a first memory cell comprising:
 a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region; and 
 a second polysilicon line and a first continuous polysilicon line over active region edge (“CPODE”) associated with a first program word line, the second polysilicon line intersecting the second active region and the first CPODE intersecting the first active region; and 
 
 a second memory cell adjacent to the first memory cell, the second memory cell comprising:
 a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region; and 
 a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the first active region and the second CPODE intersecting the second active region to form a cross-arrangement of CPODE. 
 
 
     
     
       2. The memory device of  claim 1 , further comprising a third CPODE and a fourth CPODE sandwiching the first memory cell and the second memory cell, wherein each of the third CPODE and the fourth CPODE intersect the first active region and the second active region. 
     
     
       3. The memory device of  claim 1 , further comprising a metal over diffusion layer intersecting the first active region and the second active region, wherein the metal over diffusion layer is between two adjacent read word lines. 
     
     
       4. The memory device of  claim 1 , further comprising a metal over diffusion layer intersecting the first active region and the second active region, wherein the metal over diffusion layer is between adjacent read and program word lines. 
     
     
       5. The memory device of  claim 1 , wherein the second polysilicon line and the first CPODE are spaced apart in a second direction perpendicular to a first direction in which the first active region and the second active region extend. 
     
     
       6. The memory device of  claim 1 , wherein adjacent program word lines are separated by a metal over diffusion layer that intersects either the first active region or the second active region. 
     
     
       7. The memory device of  claim 6 , wherein the adjacent program word lines are further separated by a third CPODE intersecting the first active region and the second active region. 
     
     
       8. The memory device of  claim 1 , wherein the first memory cell further comprises a fifth polysilicon line associated with a third read word line and intersecting the first active region and the second active region, and wherein the second memory cells comprises a sixth polysilicon line associated with a fourth read word line and intersecting the first active region and the second active region. 
     
     
       9. A memory cell comprising:
 a first transistor having a read word line connected to a first gate terminal of the first transistor; and 
 a second transistor having a program word line connected to a second gate terminal of the second transistor, 
 wherein the first gate terminal comprises a first polysilicon line intersecting a first active region and a second active region; 
 wherein the second gate terminal comprises a combination of a second polysilicon line intersecting the second active region and a continuous polysilicon line over active region edge (“CPODE”) intersecting the first active region; and 
 
       wherein the first active region and the second active region extend in a first direction, and the first polysilicon line, the second polysilicon line, and the CPODE extend in a second direction perpendicular to the first direction. 
     
     
       10. The memory device of  claim 9 , wherein the second polysilicon line and the CPODE are aligned and spaced apart in the second direction. 
     
     
       11. The memory device of  claim 9 , further comprising a metal over diffusion layer extending in the second direction between the first polysilicon line and the second polysilicon line and intersecting the first active region and the second active region. 
     
     
       12. The memory device of  claim 9 , further comprising a third transistor having a second read word line connected to a third gate terminal of the third transistor, wherein the third gate terminal comprises a third polysilicon line extending in the second direction and intersecting the first active region and the second active region. 
     
     
       13. The memory device of  claim 9 , further comprising an additional CPODE extending in the second direction and intersecting the first active region and the second active region. 
     
     
       14. A memory device comprising:
 a first anti-fuse memory cell comprising:
 a first polysilicon line associated with a first program word line of the first anti- fuse memory cell, wherein the first polysilicon line intersects a first active region; and 
 a first continuous polysilicon line over active region edge (“CPODE”), wherein the first CPODE intersects a second active region; and 
 
 a second anti-fuse memory cell adjacent to the first anti-fuse memory cell, the second anti-fuse memory cell comprising:
 a second polysilicon line associated with a second program word line of the second anti-fuse memory cell, wherein the second polysilicon line intersects the second active region; and 
 a second CPODE, wherein the second CPODE intersects the first active region to form a cross-arrangement of CPODE. 
 
 
     
     
       15. The memory device of  claim 14 , wherein the first anti-fuse memory cell further comprises a third polysilicon line associated with a first read word line, and wherein the third polysilicon line intersects the first active region and the second active region. 
     
     
       16. The memory device of  claim 14 , wherein the second anti-fuse memory cell further comprises a third polysilicon line associated with a second read word line, and wherein the third polysilicon line intersects the first active region and the second active region. 
     
     
       17. The memory device of  claim 14 , further comprising a third CPODE and a fourth CPODE sandwiching the first anti-fuse memory cell and the second anti-fuse memory cell, wherein each of the third CPODE and the fourth CPODE intersect the first active region and the second active region. 
     
     
       18. The memory device of  claim 14 , wherein the first polysilicon line and the first CPODE are spaced apart in a second direction perpendicular to a first direction in which the first active region and the second active region extend. 
     
     
       19. The memory device of  claim 14 , wherein adjacent program word lines are separated by a metal over diffusion layer that intersects either the first active region or the second active region. 
     
     
       20. The memory device of  claim 14 , wherein the first active region and the second active region are spaced apart in a second direction perpendicular to a first direction in which the first active region and the second active region extend.