Integrated circuit (IC) power-up testing method and device, and electronic equipment

Abstract

An integrated circuit (IC) power-up testing method, an IC power-up testing device, a storage medium and an electronic equipment are disclosed. The IC power-up testing method includes: obtaining power-up testing parameters for an IC; obtaining a plurality of power-up testing waveforms; generating a plurality of power-up test instances by conducting parameter assignments for the power-up testing waveforms based on the power-up testing parameters; and performing power-up tests on the IC using the plurality of power-up test instances. The method allows simulating various IC power-up scenarios through a plurality of power-up test instances.

The invention claimed is: 
     
       1. A power-up testing method, applicable to an integrated circuit (IC), comprising:
 obtaining power-up testing parameters for the IC; 
 obtaining a plurality of power-up testing waveforms by:
 obtaining a plurality of initial waveforms and a plurality of noise waveforms, and 
 obtaining, by superimposing the plurality of initial waveforms with the plurality of noise waveforms, the plurality of power-up testing waveforms; 
 
 generating, by conducting parameter assignments for the power-up testing waveforms based on the power-up testing parameters, a plurality of power-up test instances; and 
 performing, using the plurality of power-up test instances, power-up tests on the IC. 
 
     
     
       2. The method of  claim 1 , wherein obtaining power-up testing parameters for the IC comprises:
 obtaining a target voltage and a power-up duration for the IC. 
 
     
     
       3. The method of  claim 2 , wherein obtaining power-up testing parameters for the IC further comprises:
 obtaining a number of voltage steps for the IC. 
 
     
     
       4. The method of  claim 3 , wherein obtaining a number of voltage steps for the IC comprises:
 obtaining a maximum number and a minimum number of voltage steps; and 
 choosing a number between the maximum number and the minimum number as the number of voltage steps. 
 
     
     
       5. The method of  claim 3 , wherein generating, by conducting parameter assignments for the power-up testing waveforms based on the power-up testing parameters, a plurality of power-up test instances comprises:
 determining, based on the target voltage and the number of voltage steps, a step height of the voltage steps; 
 determining, based on the power-up duration and the number of voltage steps, a step width of the voltage steps; and 
 generating, by conducting parameter assignments for the power-up testing waveforms based on the step height and the step width, the plurality of power-up test instances. 
 
     
     
       6. The method of  claim 1 , wherein the plurality of initial waveforms and the plurality of noise waveforms are step voltage waveforms. 
     
     
       7. The method of  claim 1 , wherein each of the plurality of initial waveforms is an ascending step waveform, and each of the plurality of noise waveforms is a randomly-distributed step waveform. 
     
     
       8. The method of  claim 1 , wherein obtaining a plurality of initial waveforms and a plurality of noise waveforms comprises:
 choosing the plurality of initial waveforms and the plurality of noise waveforms from a predefined test waveform library. 
 
     
     
       9. The method of  claim 1 , wherein performing, using the plurality of power-up test instances, power-up tests on the IC comprises:
 arranging the power-up test instances into a test sequence; and 
 performing power-up tests on the IC by successively using each of the power-up test instances in the test sequence, 
 wherein, if a test result of using one of the power-up test instances in the test sequence is a failure, the power-up tests on the IC continue by using a next one of the power-up test instances in the test sequence. 
 
     
     
       10. The method of  claim 1 , wherein performing, using the plurality of power-up test instances, power-up tests on the IC comprises:
 arranging the power-up test instances into a test sequence; and 
 performing power-up tests on the IC by successively using each of the power-up test instances in the test sequence, 
 wherein, if a test result of using one of the power-up test instances in the test sequence is a failure, the power-up tests on the IC is terminated. 
 
     
     
       11. An electronic equipment, comprising:
 a processor; and 
 a memory, configured to store instructions executable by the processor, 
 wherein the processor is configured to, by executing the instructions, perform a power-up testing method applicable to an integrated circuit (IC), comprising:
 obtaining power-up testing parameters for the IC; 
 obtaining a plurality of power-up testing waveforms, wherein to obtain the plurality of power-up waveforms, the processor is further configured to perform operations, comprising:
 obtaining a plurality of initial waveforms and a plurality of noise waveforms, and 
 obtaining, by superimposing the plurality of initial waveforms with the plurality of noise waveforms, the plurality of power-up testing waveforms; 
 
 generating, by conducting parameter assignments for the power-up testing waveforms based on the power-up testing parameters, a plurality of power-up test instances; and 
 performing, using the plurality of power-up test instances, power-up tests on the IC. 
 
 
     
     
       12. The equipment of  claim 11 , wherein, when obtaining power-up testing parameters for the IC, the processor is further configured to:
 obtain a target voltage and a power-up duration for the IC. 
 
     
     
       13. The equipment of  claim 12 , wherein, when obtaining power-up testing parameters for the IC, the processor is further configured to:
 obtain a number of voltage steps for the IC. 
 
     
     
       14. The equipment of  claim 13 , wherein, to obtain a number of voltage steps for the IC, the process is further configured to:
 obtain a maximum number and a minimum number of voltage steps; and 
 choose a number between the maximum number and the minimum number as the number of voltage steps. 
 
     
     
       15. The equipment of  claim 13 , wherein, when generating a plurality of power-up test instances, the processor is further configured to:
 determine, based on the target voltage and the number of voltage steps, a step height of the voltage steps; 
 determine, based on the power-up duration and the number of voltage steps, a step width of the voltage steps; and 
 generate, by conducting parameter assignments for the power-up testing waveforms based on the step height and the step width, the plurality of power-up test instances. 
 
     
     
       16. The equipment of  claim 11 , wherein the plurality of initial waveforms and the plurality of noise waveforms are step voltage waveforms. 
     
     
       17. The equipment of  claim 11 , wherein each of the plurality of initial waveforms is an ascending step waveform, and each of the plurality of noise waveforms is a randomly-distributed step waveform.