Contact layer traces to program programmable ROM

Abstract

A device includes a programmable ROM circuit, an address circuit, and a processor. The programmable ROM circuit includes multiple physically contiguous pairs of bit-cells, each pair of bit-cells includes an active layer trace extending continuously across both of the bit-cells, each pair of bit-cells comprises a shared contact layer point when the pair of bit-cells is programmed to a value of one and no shared contact layer point when the pair of bit-cells is programmed to a value of zero. The address circuit is coupled to the programmable ROM circuit and configured to address only a first bit-cell of each pair of bit-cells. The processor is coupled to the address circuit and the programmable ROM circuit and configured to use the address circuit to read data from one or more pairs of bit-cells of the programmable ROM circuit.

What is claimed is: 
     
       1. A device comprising:
 a programmable read-only memory (ROM) circuit, comprising:
 physically contiguous pairs of bit-cells, each pair of bit-cells including an active layer trace extending continuously across both of the bit-cells of the pair of bit-cells, wherein the pairs of bit-cells include: 
 a first pair of bit-cells comprising a contact layer point shared among the bit-cells in the first pair such that each bit-cell in the pair is programmed to a value of one; and 
 a second pair of bit-cells that comprises no contact layer point shared among the bit-cells in the second pair such that each bit-cell in the pair is programmed to a value of zero; 
 
 an address circuit coupled to the programmable ROM circuit and configured to address only a first bit-cell of each pair of bit-cells; and 
 a processor coupled to the address circuit and the programmable ROM circuit, the processor configured to use the address circuit to read data from the pairs of bit-cells of the programmable ROM circuit. 
 
     
     
       2. The device of  claim 1 , wherein:
 the multiple physically contiguous pairs of bit-cells comprise a plurality of non-overlapping byte-subsets of the pairs of bit-cells, each byte-subset comprising n pairs of bit-cells; 
 the address circuit is configured to address simultaneously the first bit-cell of each pair of bit-cells in a selected byte-subset; and 
 the processor is configured to read data simultaneously from the first bit-cell of each pair of bit-cells in the selected byte-subset. 
 
     
     
       3. The device of  claim 2 , wherein the pairs of bit-cells of at least one byte-subset are arranged in a column. 
     
     
       4. The device of  claim 3 , wherein two or more of the plurality of byte-subsets are arranged in a row. 
     
     
       5. The device of  claim 4 , wherein the active layer trace across both of the bit-cells of a first pair of bit-cells of a first byte-subset in the row extends continuously across both of the bit-cells of a second pair of bit-cells of a second byte-subset in the row. 
     
     
       6. The device of  claim 2 , wherein the number n of pairs of bit-cells of at least one byte-subset is four. 
     
     
       7. The device of  claim 6 , wherein the programmable ROM circuit comprises one of sixteen byte-subsets and thirty-two byte-subsets. 
     
     
       8. The device of  claim 2 , wherein:
 the programmable ROM circuit comprises a first group of byte-subsets and a second group of byte-subsets; 
 bit-cell addresses of the first bit-cell of each pair of bit-cells of the first group of byte-subsets are contiguous; 
 bit-cell addresses of the first bit-cell of each pair of bit-cells of the second group of byte-subsets are contiguous; and 
 a first bit-cell address range of the first bit-cell of each pair of bit-cells of the first group of byte-subsets is discontiguous from a second bit-cell address range of the first bit-cell of each pair of bit-cells of the second group of byte-subsets. 
 
     
     
       9. A device comprising:
 a programmable read-only memory (ROM) circuit, comprising:
 a first plurality of bit-cells comprising multiple non-overlapping single-cell byte-subsets of the bit-cells, each single-cell byte-subset comprising m bit-cells; 
 a second plurality of bit-cells comprising multiple physically contiguous pairs of bit-cells, each pair of bit-cells including an active layer trace extending continuously across both of the bit-cells of the pair of bit-cells; 
 a first pair of bit-cells comprising a contact layer point shared among the bit-cells in the first pair such that each bit-cell in the pair is programmed to a value of one; and 
 a second pair of bit-cells that comprises no contact layer point shared among the bit-cells in the second pair such that each bit-cell in the pair is programmed to a value of zero; 
 the multiple physically contiguous pairs of bit-cells comprising a plurality of non-overlapping paired-cell byte-subsets of the pairs of bit-cells, each paired-cell byte-subset comprising n pairs of bit-cells; 
 
 an address circuit coupled to the programmable ROM circuit and configured to address simultaneously the bit-cells of a selected single-cell byte-subset or only a first bit-cell of each pair of bit-cells of a selected paired-cell byte-subset; and 
 a processor coupled to the address circuit and the programmable ROM circuit, the processor configured to use the address circuit to read data from the selected single-cell byte-subset or selected paired-cell byte-subset of the programmable ROM circuit. 
 
     
     
       10. The device of  claim 9 , wherein the bit-cells of at least one single-cell byte-subset are arranged in a first column and the pairs of bit-cells of at least one paired-cell byte-subset are arranged in a second column. 
     
     
       11. The device of  claim 10 , wherein two or more of the single-cell byte-subsets are arranged in a first row and two or more of the paired-cell byte-subsets are arranged in a second row. 
     
     
       12. The device of  claim 11 , wherein the active layer trace across both of the bit-cells of a first pair of bit-cells of a first paired-cell byte-subset in the second row extends continuously across both of the bit-cells of a second pair of bit-cells of a second paired-cell byte-subset in the second row. 
     
     
       13. The device of  claim 9 , wherein the number m of bit-cells of at least one single-cell byte-subset is four or the number n of pairs of bit-cells of at least one paired-cell byte-subset is four. 
     
     
       14. The device of  claim 9 , wherein:
 the programmable ROM circuit comprises a first group of paired-cell byte-subsets and a second group of paired-cell byte-subsets; 
 bit-cell addresses of the first bit-cell of each pair of bit-cells of the first group of paired-cell byte-subsets are contiguous and bit-cell addresses of the first bit-cell of each pair of bit-cells of the second group of paired-cell byte-subsets are contiguous; and 
 a first bit-cell address range of the first bit-cell of each pair of bit-cells of the first group of paired-cell byte-subsets is discontiguous from a second bit-cell address range of the first bit-cell of each pair of bit-cells of the second group of paired-cell byte-subsets. 
 
     
     
       15. A method, comprising:
 initiating fabrication of a first system on a chip (SoC) based on a first Graphic Design System Information Interchange (GDSII) chip layout file, the first GDSII chip layout file defining the first SoC as comprising a programmable read-only memory (ROM) circuit that includes:
 multiple physically contiguous pairs of bit-cells, each pair of bit-cells including an active layer trace extending continuously across both of the bit-cells of the pair of bit-cells; and 
 each pair of bit-cells comprising a contact layer point shared among the bit-cells in the pair when each bit-cell in the pair is programmed to a value of one and no contact layer point shared among the bit-cells in the pair when each bit-cell in the pair is programmed to a value of zero; 
 
 testing the first SoC; 
 in response to determining that firmware of the first SoC should be changed;
 halting fabrication of the first SoC; 
 generating a new ROM image; 
 initiating generation of a second GDSII chip layout file defining a second SoC that differs from the first GDSII chip layout file at least in locations of the shared contact layer points of the pairs of bit-cells of the programmable ROM circuit in the first SoC and in the second SoC; and 
 initiating fabrication of the second SoC based on the second GDSII chip layout file. 
 
 
     
     
       16. The method of  claim 15 , wherein the second SoC is fabricated from a partially fabricated first SoC that has not had a contact layer deposited in the programmable ROM circuit. 
     
     
       17. The method of  claim 15 , wherein the first and second GDSII chip layout files define:
 a plurality of non-overlapping byte-subsets of the pairs of bit-cells, each byte-subset comprising n pairs of bit-cells; 
 an address circuit configured to address simultaneously a first bit-cell of each pair of bit-cells in a selected byte-subset; and 
 a processor configured to read data simultaneously from the first bit-cell of each pair of bit-cells in the selected byte-subset. 
 
     
     
       18. The method of  claim 17 , wherein the first and second GDSII chip layout files define:
 the pairs of bit-cells of at least one byte-subset as arranged in a column; 
 two or more of the plurality of byte-subsets as arranged in a row; and 
 the active layer trace across both of the bit-cells of a first pair of bit-cells of a first byte-subset in the row as extending continuously across both of the bit-cells of a second pair of bit-cells of a second byte-subset in the row. 
 
     
     
       19. The method of  claim 17 , wherein the first and second GDSII chip layout files define the number n of pairs of bit-cells of each byte-subset as four. 
     
     
       20. The method of  claim 17 , wherein the first and second GDSII chip layout files define:
 the programmable ROM circuit as comprising a first group of paired-cell byte-subsets and a second group of paired-cell byte-subsets; 
 the first bit-cell of each pair of bit-cells of the first group of paired-cell byte-subsets as having contiguous bit-cell addresses; 
 the first bit-cell of each pair of bit-cells of the second group of paired-cell byte-subsets as having contiguous bit-cell addresses; and 
 a first bit-cell address range of the first bit-cell of each pair of bit-cells of the first group of paired-cell byte-subsets discontiguous from a second bit-cell address range of the first bit-cell of each pair of bit-cells of the second group of paired-cell byte-subsets.