Systems and methods for fabricating FinFETs with different threshold voltages

Abstract

Systems and methods are provided for fabricating semiconductor device structures on a substrate. A first fin structure is formed on a substrate. A second fin structure is formed on the substrate. A first semiconductor material is formed on both the first fin structure and the second fin structure. A second semiconductor material is formed on the first semiconductor material on both the first fin structure and the second fin structure. The first semiconductor material on the first fin structure is oxidized to form a first oxide. The second semiconductor material on the first fin structure is removed. A first dielectric material and a first electrode are formed on the first fin structure. A second dielectric material and a second electrode are formed on the second fin structure.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a first device including a first fin structure on a substrate, a first semiconductor layer made of a first semiconductor material and disposed on the first fin structure, a first gate dielectric layer on the first semiconductor layer, and a first gate electrode on the first gate dielectric layer; and 
 a second device including a second fin structure on the substrate, a second semiconductor layer made of the first semiconductor material and disposed on the second fin structure, a third semiconductor layer on the second semiconductor layer, a second gate dielectric layer on the third semiconductor layer, and a second gate electrode on the second gate dielectric layer, 
 wherein an oxide of the first semiconductor material is formed on side portions of the second semiconductor layer, and 
 the oxide is separated from the second gate dielectric layer. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein:
 the first semiconductor layer has a convex-shaped portion, and 
 the first gate dielectric layer is formed on the convex-shaped portion of the first semiconductor layer. 
 
     
     
       3. The semiconductor device of  claim 1 , wherein the oxide surrounds the second semiconductor layer. 
     
     
       4. The semiconductor device of  claim 1 , further comprising an isolation dielectric layer in which the first and second fin structures are embedded,
 wherein an upper surface of the first semiconductor layer and an upper surface of the second semiconductor layer are located below an upper surface of the isolation dielectric layer. 
 
     
     
       5. The semiconductor device of  claim 4 , wherein:
 the second gate dielectric layer is disposed on the upper surface of the isolation dielectric layer, and 
 a top of the oxide is located below a bottom of the gate dielectric layer. 
 
     
     
       6. The semiconductor device of  claim 4 , wherein a bottom of the first gate electrode is located below the upper surface of the isolation dielectric layer. 
     
     
       7. The semiconductor device of  claim 1 , wherein the first semiconductor material contains at least germanium. 
     
     
       8. The semiconductor device of  claim 7 , wherein the oxide is germanium oxide or silicon germanium oxide. 
     
     
       9. A semiconductor device comprising:
 a first fin structure on a substrate; 
 an isolation dielectric layer in which the first fin structure is embedded; 
 a first semiconductor layer made of a first semiconductor material and disposed on the first fin structure; 
 a first gate dielectric layer on the first semiconductor layer and continuously covering an uppermost surface and side surfaces of the first semiconductor layer; 
 a first gate electrode on the first gate dielectric layer; and 
 an interlayer dielectric layer on the isolation dielectric layer, 
 wherein an entirety of the first semiconductor layer is located below an interface between the isolation dielectric layer and the interlayer dielectric layer, 
 a width of the uppermost surface of the first semiconductor layer is smaller than a width of a bottom surface of the first semiconductor layer, and 
 a part of the first gate dielectric layer is penetrates into the isolation dielectric layer. 
 
     
     
       10. The semiconductor device of  claim 9 , wherein a bottom of the first gate dielectric layer is located below the interface. 
     
     
       11. The semiconductor device of  claim 9 , wherein a bottom of the first gate electrode is located below the interface. 
     
     
       12. The semiconductor device of  claim 9 , wherein:
 the first semiconductor layer has a convex-shaped portion, and 
 the first gate dielectric layer is formed on the convex-shaped portion of the first semiconductor layer. 
 
     
     
       13. A semiconductor device comprising:
 a fin structure on a substrate; 
 a first semiconductor layer made of a first semiconductor material and disposed on the fin structure; 
 a second semiconductor layer made of a second semiconductor material and disposed on the first semiconductor layer; 
 a gate dielectric layer on the second semiconductor layer; and 
 a gate electrode on the gate dielectric layer, 
 wherein an oxide of the first semiconductor material is formed on side portions of the first semiconductor layer, and 
 the oxide is separated from the gate dielectric layer. 
 
     
     
       14. The semiconductor device of  claim 13 , wherein the oxide surrounds the first semiconductor layer. 
     
     
       15. The semiconductor device of  claim 13 , further comprising an isolation dielectric layer in which the fin structure is embedded,
 wherein an upper surface of the first semiconductor layer is located below an upper surface of the isolation dielectric layer. 
 
     
     
       16. The semiconductor device of  claim 15 , wherein the gate dielectric layer is disposed on the upper surface of the isolation dielectric layer. 
     
     
       17. The semiconductor device of  claim 13 , wherein the first semiconductor material contains at least germanium. 
     
     
       18. The semiconductor device of  claim 17 , wherein the oxide is germanium oxide or silicon germanium oxide. 
     
     
       19. The semiconductor device of  claim 13 , wherein the second semiconductor layer protrudes from the isolation dielectric layer. 
     
     
       20. The semiconductor device of  claim 13 , wherein the oxide has a largest thickness at a center portion in a vertical direction.