Configurable logic platform with reconfigurable processing circuitry

Abstract

A configurable logic platform may include a physical interconnect for connecting to a processing system, first and second reconfigurable logic regions, a configuration port for applying configuration data to the first and second reconfigurable logic regions, and a reconfiguration logic function accessible via transactions of the physical interconnect, the reconfiguration logic function providing restricted access to the configuration port from the physical interconnect. The platform may include a first interface function providing an interface to the first reconfigurable logic region and a second interface function providing an interface to the first reconfigurable logic region. The first and second interface functions may allow information to be transmitted over the physical interconnect and prevent the respective reconfigurable logic region from directly accessing the physical interconnect. The platform may include logic configured to apportion bandwidth of the physical interconnect among the interface functions.

What is claimed is: 
     
       1. A configurable logic platform comprising:
 a physical interconnect for connecting the configurable logic platform to a processor; 
 a first reconfigurable logic region comprising logic blocks that are configured based on first configuration data corresponding to the first reconfigurable logic region; 
 a second reconfigurable logic region comprising logic blocks that are configured based on second configuration data corresponding to the second reconfigurable logic region; 
 a configuration port for applying the first and second configuration data to the first and second reconfigurable logic regions so that the first reconfigurable logic region is configured based on the first configuration data corresponding to the first reconfigurable logic region and the second reconfigurable logic region is configured based on the second configuration data corresponding to the second reconfigurable logic region; 
 a reconfiguration logic function accessible via transactions of the physical interconnect, the reconfiguration logic function in communication with the configuration port, the reconfiguration logic function providing restricted access to the configuration port from the physical interconnect; 
 a first interface function accessible via transactions of the physical interconnect, the first interface function providing an interface to the first reconfigurable logic region which allows information to be transmitted over the physical interconnect and prevents the first reconfigurable logic region from directly accessing the physical interconnect; 
 a second interface function accessible via transactions of the physical interconnect, the second interface function providing an interface to the second reconfigurable logic region which allows information to be transmitted over the physical interconnect and prevents the second reconfigurable logic region from directly accessing the physical interconnect; and 
 logic configured to apportion bandwidth of the physical interconnect among at least the first interface function and the second interface function. 
 
     
     
       2. The configurable logic platform of  claim 1 , further comprising transfer logic configured to provide a first communication path between the first reconfigurable logic region and a common memory and a second communication path between the second reconfigurable logic region and the common memory. 
     
     
       3. The configurable logic platform of  claim 2 , wherein:
 the transfer logic is configured to restrict access by the first reconfigurable logic region to addresses of the common memory within a first address range; and 
 the transfer logic is configured to restrict access by the second reconfigurable logic region to addresses of the common memory within a second address range. 
 
     
     
       4. The configurable logic platform of  claim 2 , wherein
 the transfer logic is configured to restrict the first reconfigurable logic region to a first amount of bandwidth for transfers between the common memory and the first reconfigurable logic region; and 
 the transfer logic is configured to restrict the second reconfigurable logic region to a second amount of bandwidth for transfers between the common memory and the second reconfigurable logic region. 
 
     
     
       5. A server computer comprising:
 a central processing unit; and 
 a configurable logic platform connected to the central processing unit, the configurable logic platform comprising
 a physical interconnect for connecting the configurable logic platform to the central processing unit, 
 a first reconfigurable logic region comprising logic blocks that are configured based on first configuration data corresponding to the first reconfigurable logic region, 
 a second reconfigurable logic region comprising logic blocks that are configured based on second configuration data corresponding to the second reconfigurable logic region, 
 a configuration port for applying the first and second configuration data to the first and second reconfigurable logic regions so that the first reconfigurable logic region is configured based on the first configuration data corresponding to the first reconfigurable logic region and the second reconfigurable logic region is configured based on the second configuration data corresponding to the second reconfigurable logic region, 
 a reconfiguration logic function accessible via transactions of the physical interconnect, the reconfiguration logic function in communication with the configuration port, the reconfiguration logic function providing restricted access to the configuration port from the physical interconnect, 
 a first interface function accessible via transactions of the physical interconnect, the first interface function providing an interface to the first reconfigurable logic region which allows information to be transmitted over the physical interconnect and prevents the first reconfigurable logic region from directly accessing the physical interconnect, 
 a second interface function accessible via transactions of the physical interconnect, the second interface function providing an interface to the second reconfigurable logic region which allows information to be transmitted over the physical interconnect and prevents the second reconfigurable logic region from directly accessing the physical interconnect, and 
 arbitration logic configured to apportion bandwidth of the physical interconnect among at least the first interface function and the second interface function. 
 
 
     
     
       6. The server computer of  claim 5 , wherein the configurable logic platform further comprises transfer logic configured to provide a first communication path between the first reconfigurable logic region and a first memory region of a common memory and a second communication path between the second reconfigurable logic region and the common memory. 
     
     
       7. The server computer of  claim 6 , wherein:
 the transfer logic is configured to restrict access by the first reconfigurable logic region to addresses of the common memory within a first address range; and 
 the transfer logic is configured to restrict access by the second reconfigurable logic region to addresses of the common memory within a second address range. 
 
     
     
       8. The server computer of  claim 6 , wherein:
 the transfer logic is configured to restrict the first reconfigurable logic region to a first amount of bandwidth for transfers between the common memory and the first reconfigurable logic region; and 
 the transfer logic is configured to restrict the second reconfigurable logic region to a second amount of bandwidth for transfers between the transfer logic and the second reconfigurable logic region. 
 
     
     
       9. Hardware logic comprising:
 a physical interconnect for connecting the hardware logic to a processor; 
 a first reconfigurable logic region comprising logic blocks that are configured based on first configuration data corresponding to the first reconfigurable logic region; 
 a second reconfigurable logic region comprising logic blocks that are configured based on second configuration data corresponding to the second reconfigurable logic region; 
 a configuration port for applying the first and second configuration data to the first and second reconfigurable logic regions so that the first reconfigurable logic region is configured based on the first configuration data corresponding to the first reconfigurable logic region and the second reconfigurable logic region is configured based on the second configuration data corresponding to the second reconfigurable logic region; 
 a reconfiguration logic function accessible via transactions of the physical interconnect, the reconfiguration logic function in communication with the configuration port, the reconfiguration logic function providing restricted access to the configuration port from the physical interconnect; 
 a first interface function accessible via transactions of the physical interconnect, the first interface function providing an interface to the first reconfigurable logic region which allows information to be transmitted over the physical interconnect and prevents the first reconfigurable logic region from directly accessing the physical interconnect; 
 a second interface function accessible via transactions of the physical interconnect, the second interface function providing an interface to the second reconfigurable logic region which allows information to be transmitted over the physical interconnect and prevents the second reconfigurable logic region from directly accessing the physical interconnect; and 
 logic configured to apportion bandwidth of the physical interconnect among at least the first interface function and the second interface function. 
 
     
     
       10. The hardware logic of  claim 9 , further comprising transfer logic configured to provide a first communication path between the first reconfigurable logic region and a first memory region of a common memory and a second communication path between the second reconfigurable logic region and the common memory. 
     
     
       11. The hardware logic of  claim 10 , wherein:
 the transfer logic is configured to restrict access by the first reconfigurable logic region to addresses of the common memory within a first address range; and 
 the transfer logic is configured to restrict access by the second reconfigurable logic region to addresses of the common memory within a second address range. 
 
     
     
       12. The hardware logic of  claim 10 , wherein:
 the transfer logic is configured to restrict the first reconfigurable logic region to a first amount of bandwidth for transfers between the common memory and the first reconfigurable logic region; and 
 the transfer logic is configured to restrict the second reconfigurable logic region to a second amount of bandwidth for transfers between the transfer logic and the second reconfigurable logic region.