Semiconductor device structure with fine patterns at different levels and method for forming the same

Abstract

The present disclosure provides a semiconductor device structure with fine patterns at different levels and a method for forming the semiconductor device structure, which can prevent the collapse of the fine patterns and reduces the parasitic capacitance between fine patterns The semiconductor device structure includes a substrate; a first target structure disposed over the substrate, wherein the first target structure comprises a first portion, a second portion, and a third portion, a height of the first portion and a height of the second portion are greater than a height of the third portion; a second target structure disposed over the target layer, wherein the second target structure comprises a fourth portion, a fifth portion, and a sixth portion: a low-level conductive pattern positioned between the first target structure and the second target structure; and a high-level conductive pattern positioned in the first target structure.

What is claimed is: 
     
       1. A semiconductor device structure, comprising:
 a substrate; 
 a first target structure disposed over the substrate, wherein the first target structure comprises a first portion, a second portion, and a third portion connected to the first portion and the second portion, a height of the first portion and a height of the second portion are greater than a height of the third portion; 
 a second target structure disposed over the substrate, wherein the second target structure comprises a fourth portion, a fifth portion, and a sixth portion connected to the fourth portion and the fifth portion; 
 a low-level conductive pattern positioned between the first target structure and the second target structure; 
 a high-level conductive pattern positioned on the first target structure; 
 a first tall air gap between the first target structure and the low-level conductive pattern; 
 a second tall air gap between the second target structure and the low-level conductive pattern; 
 a third tall air gap, wherein the first tall air gap is positioned on a sidewall of the second portion, and the third tall air gap is positioned on a sidewall of the first portion; and 
 wherein the first tall air gap and the second tall air gap have a thickness substantially identical to a thickness of the lower-level conductive pattern. 
 
     
     
       2. The semiconductor device structure of  claim 1 , wherein the low-level conductive pattern has a first top end and first bottom end, the high-level conductive pattern has a second top end and second bottom end, the first bottom end is lower than the second bottom end, and the first top end and the second top end are substantially at the same level. 
     
     
       3. The semiconductor device structure of  claim 1 , wherein the first tall air gap and the second tall air gap have spacer profiles in a cross-sectional view. 
     
     
       4. The semiconductor device structure of  claim 1 , wherein the first tall air gap and the second tall air gap are substantially symmetric with respect to a middle line between the first target structure and the second target structure. 
     
     
       5. The semiconductor device structure of  claim 1 , wherein the first tall air gap and the third tall air gap are substantially symmetric with respect to a middle line between the first portion and the second portion. 
     
     
       6. The semiconductor device structure of  claim 1 , further comprising a first tall dielectric spacer positioned between the first tall air gap and the low-level conductive pattern, and a second tall dielectric spacer positioned between the second tall air gap and the low-level conductive pattern. 
     
     
       7. The semiconductor device structure of  claim 6 , further comprising a first short air gap and a first short dielectric spacer positioned between the first tall air gap and the high-level conductive pattern. 
     
     
       8. The semiconductor device structure of  claim 1 , wherein the high-level conductive pattern is positioned between the first portion and the second portion. 
     
     
       9. The semiconductor device structure of  claim 8 , further comprising, and a short air gap positioned between the high-level conductive pattern and the second portion. 
     
     
       10. The semiconductor device structure of  claim 9 , wherein the tall air gap and the short air gap have spacer profiles in a cross-sectional view. 
     
     
       11. The semiconductor device structure of  claim 1 , wherein the first portion and the second portion are substantially symmetric with respect to a middle line between the first portion and the second portion. 
     
     
       12. A semiconductor device structure, comprising:
 a substrate; 
 a first target structure disposed over the substrate, wherein the first target structure comprises a first portion, a second portion, and a third portion connected to the first portion and the second portion, a height of the first portion and a height of the second portion are greater than a height of the third portion; 
 a second target structure disposed over the substrate, wherein the second target structure comprises a fourth portion, a fifth portion, and a sixth portion connected to the fourth portion and the fifth portion; 
 a low-level conductive pattern positioned between the first target structure and the second target structure; 
 a high-level conductive pattern positioned in the first target structure; 
 a first short air gap and a second short air gap positioned at two sides of the high-level conductive pattern, wherein the first short air gap and the second short air gap have a thickness substantially identical to a thickness of the high-level conductive pattern; and 
 a tall air gap positioned between the low-level conductive pattern and the second portion. 
 
     
     
       13. The semiconductor device structure of  claim 12 , wherein the first short air gap and the second short air gap are substantially symmetric with respect to a middle line between the first portion and the second portion.